SKU51 Zipcores

BFSK DEMOD Binary-FSK Demodulator Rev. 1.5 Key Design Features Block Diagram Technology independent IP Core for FPGA and ASIC Supplied as human readable VHDL (or Verilog) source code filter type 32 16-bit signed input data samples I i in LPF Accepts either complex (I/Q) or real input samples 16 mag out Programmable mark / space frequencies q in 16 (optional) MAG Choice of low pass filter responses COMPLEX DIGITAL 16 MIXER Carrier separation ~ symbol rate or greater Q LPF Practical symbol rates of up to 10 Mbits/s fsk val SYMBOL phase inc0 (space freq.) DECODE Baseband or passband operation CMP AND phase inc1 (mark freq.) TIMING 1 RECOVERY Typical FPGA sample rates of up to 200 MHz fsk out I LPF Connects directly to an external ADC 16 16 Applications MAG COMPLEX en DIGITAL MIXER Q Software radio clk LPF Short range telemetry reset filter type SRD and ISM band devices Low cost RF applications for FPGA Figure 1: FSK demodulator architecture Generic Parameters Pin-out Description Generic name Description Type Valid range gain Internal gain setting integer 0: x 1 Pin name I/O Description Active state (compensates for low 1: x 2 clk in Sample clock rising edge amplitude input 2: x 4 signals) 3: x 8 reset in Asynchronous reset low 32 seed Seed for random std logic 0 < seed < 2 en in clock enable high number generator in vector phase inc0 31:0 in Phase increment as an data DDS component unsigned 32-bit number dithering Enable phase boolean TRUE / FALSE (f centre frequency) 0 dithering in DDS phase inc1 31:0 in Phase increment as an data use complex Enable complex or boolean TRUE: unsigned 32-bit number real data samples use both ports (f centre frequency) 1 i in and q in i in 15:0 in Real (In-phase) input data as 16-bit signed FALSE: use port q in 15:0 in Imaginary (Quadrature) data i in only input as 16-bit signed (optional input) filter type Low-pass filter integer 0: min B/W response type 3: max B/W mag out 15:0 out Magnitude of symbols after data compare block as 16-bit sym period Symbol period in integer 0 to 65535 signed sample clocks fsk val out FSK bit valid strobe high sym polarity Swaps symbol polarity boolean TRUE / FALSE i.e. 1 0 fsk out out FSK bit out data 1 Xilinx 7-series used as a benchmark Copyright 2016 www.zipcores.com Download this VHDL Core Page 1 of 5 gain seed dithering use complex sym period sym polarityBFSK DEMOD Binary-FSK Demodulator Rev. 1.5 Low pass I/Q filters General Description The I and Q signal paths are filtered using a pair of low pass IIR filters. In BFSK DEMOD is a precision Binary-FSK Demodulator IP Core based on total, there are four separate filter responses that may be selected using a non-coherent receiver design. The demodulator is fully programmable, the generic parameter filter type. allowing for a varied range of symbol rates and mark/space tone frequencies. Input data samples may be either complex or real for Note that for the best possible results, it is important that the full 16-bit support of either passband or baseband signals. The module allows easy dynamic range of the IIR filters is used. In the case of low amplitude input connectivity to an external ADC with up to 16-bit signed input samples. signals, the generic parameter gain may be adjusted to increase the amplitudes of the I and Q signals out of the DDC. Figure 2 shows the Figure 1 shows the basic architecture in more detail. The mark and space different filter responses available. tone frequencies are generated by a pair of precision local oscillators. Each oscillator is implemented as a DDS with an SFDR of better than 80 dBs and a theoretical SNR of approximately 100 dBs. After mixing, the I and Q signal paths for each tone are filtered to remove components above the mark and space centre frequencies. The characteristics of these filters may be changed depending on the desired FSK signal bandwidth. A power function is used to compute the relative magnitudes of the mark/space tones after filtering. These magnitudes are then compared and passed to the symbol decode and timing recovery circuit. The signal mag out is a 16-bit signed output that allows the user to monitor the magnitude of the output symbols before decode and timing recovery. The demodulated FSK bit-stream appears at the output fsk out. Bits are valid on the rising edge of clk when fsk val is high. Mark and Space centre frequencies The frequencies of the mark and space tones are controlled by the signals phase inc0 and phase inc1. The phase increment may be calculated using the formula: 32 =(F 2 )/ F INC OUT S Where F is the desired oscillator frequency and F is the sampling OUT S frequency. When the desired oscillator frequency is negative (e.g. for baseband operation) then the formula becomes: 32 =((F F )2 )/ F INC S OUT S Note that an integer value for the phase increment must be used. As an example, consider a 100 MHz sample clock with a desired local oscillator frequency of 6.197 MHz. The phase increment would be calculated as 32 (6.197 * 2 ) / 100 = 266159123. The minimum and maximum local oscillator frequencies are given by the following formulas: 32 F = F / 2 , F = F / 2 MIN S MAX S Figure 2: Low-pass filter responses. The -3dB cutoff points are: (a) 0.005, (b) 0.01, (c) 0.02 and (d) 0.03 rads/sample As an example, a 100 MHz sample clock would allow a minimum local oscillator frequency of 0.0233 Hz. Conversely, the maximum frequency the local oscillator can generate is given by the Nyquist-Shannon Filter (a) is characterized by a very narrow bandwidth and a long impulse sampling theorem (Fs/2). response time. Conversely, filter (d) has the widest bandwidth but a shorter impulse response time. The table below outlines the different filter 2 characteristics in more detail . 2 A range of different filter responses are available on request. Please contact Zipcores for more details. Copyright 2016 www.zipcores.com Download this VHDL Core Page 2 of 5