VID FRAME BUFFER Video Frame Buffer IP Core Rev. 2.0 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, 16/24/32 16/24/32 ASIC or SoC etc. etc. pixin pixout pixin sof pixout vsync Frame Sync Supplied as human readable VHDL (or Verilog) source code Input Output pixin val pixout hsync Aligner Regeneration Regs Regs pixout val Output supports full flow control permitting output pixels to be pixout rdy stalled (or even whole frames if necessary) 1 Supports any video resolution 128-bit 128-bit Pixel Pixel Support for RGB or YCbCr pixel formats Unpack Pack Input pixel FIFO Output pixel FIFO Includes frame skip and frame repeat functionality to compensate for different input and output frame rates clk fb proc Generic 128-bit external memory interface with configurable reset FRAME fb skip burst size BUFFER fb repeat Diagnostic bits per pixel CONTROLLER flags fb err ovfl1 pixels per line fb err ovfl2 Linear memory bursts minimise page-breaks in synchronous lines per frame fb err uflow memory architectures words per frame Memory Memory Write Burst Read Burst Ideal for interfacing to all types of memory such as SRAM, mem start addr Controller Controller mem burst size SDRAM, DDR, DDR2, DDR3, DDR4 etc. mem frame repeat 2 Supports 300 MHz+ operation on basic FPGA devices Memory Read/Write Arbiter 128 128 Applications Buffering video frames in external memory Real-time digital video applications GENERIC MEMORY INTERFACE Video genlock applications Adapting to different pixel-clock rates and frame rates Figure 1: Video Frame Buffer architecture Essential component in video processing pipelines Pin-out Description Generic Parameters SYSTEM SIGNALS Pin name I/O Description Active state Generic name Description Type Valid range clk in Synchronous system rising edge bits per pixel (bbp) Input video bits integer 16, 24 or 32 clock per pixel reset in Asynchronous system low mem start addr Start address in integer 0 reset memory of frame fb proc out Frame processed high buffer strobe (128-bit aligned) fb skip out Frame skip strobe high-pulse mem burst size Size of memory integer 2 read / write burst fb repeat out Frame repeat strobe high-pulse (in 128-bit words) (when repeat enabled) mem frame repeat Enable / disable boolean True/False fb err ovfl1 out Input FIFO overflow high frame repeat error mode fb err ovfl2 out Output FIFO overflow high error fb err uflow out Output pixel underflow high flag 1 External memory permitting 2 Xilinx 7-series used as a benchmark Copyright 2017 www.zipcores.com Download this IP Core Page 1 of 7 mem rw mem wdata mem addr mem addr val mem addr rdy mem rdata mem rdata valVID FRAME BUFFER Video Frame Buffer IP Core Rev. 2.0 INPUT VIDEO INTERFACE General Description Pin name I/O Description Active state pixin in Input pixel data The VID FRAME BUFFER (VFB) IP Core is a high-speed multi-format bits per pixel - 1:0 video frame buffer that samples an input video stream and buffers it in an external memory. The VFB is capable of very high-speed operation - pixin sof in Start of frame flag high achieving over 300 MHz on standard FPGA platforms. (coincident with first pixel in frame) The VFB will automatically adapt to different input and output frame rates. pixin val in Input pixel valid high If the input frame rate is too high, then the VFB will drop or skip an input frame. Likewise, if the output frame rate is higher than the input frame 3 rate, then frames will be repeated . The result is a system that seamlessly adapts to the different frame rates at the input and output of PROGRAMMABLE INPUT VIDEO PARAMETERS the VFB. Pin name I/O Description Active state The memory port is a generic 128-bit read/write interface that may be pixels per line (ppl) in Number of pixels in data connected to a wide variety of memory types and memory controllers. 15:0 each line of input Memory read/write requests are sent as a sequential linear burst that is video optimized for transfers over synchronous memory. lines per frame (lpf) in Number of lines in data 15:0 each frame of input By using a series of VFB IP Cores in parallel, multiple video-sources may video be synchronized together. Figure 1. shows the architecture of the Video Frame Buffer in more detail. words per frame in Size of one frame in data 31:0 128-bit words (ppl * lpf * bbp) / 128 Input video interface OUTPUT VIDEO INTERFACE The VFB supports any input pixel format as long as the pixels are aligned Pin name I/O Description Active state to a 16, 24 or 32-bit word boundary. Input pixels are sampled on the rising-edge of the system clock when pixin val is high. The signal pixout out Output pixel data pixin sof is an active high flag that is coincident with the first pixel of the bits per pixel - 1:0 input frame. pixout vsync out Vertical sync flag high Note that the input video interface is free running and non-stallable. If the (coincident with first input frame rate is too high for the available memory bandwidth, then pixel in frame) input frames will be dropped. pixout hsync out Horizontal sync flag high (coincident with first pixel in line) Output video interface pixout val out Output pixel valid high pixout rdy in Ready to accept high Pixels flow out of the VFB in accordance with the valid-ready pipeline output pixel protocol. This protocol is used by all Zipcores video IP, and allows for (handshake signal) simple connectivity between modules. Output pixels and syncs are transferred out of the VFB on the rising edge of the system clock when pixin val and pixin rdy are both high. In GENERIC 128-BIT MEMORY INTERFACE addition, the output may be stalled, allowing pixels (or even whole frames) Pin name I/O Description Active state to be held back by asserting pixout rdy low. In order to identify the boundary between frames and lines, the sync signals pixout vsync and mem rw out Memory read / write 0: write pixout hsync are provided. The vsync signal is asserted with the first flag 1: read output pixel of a frame and the hsync signal is asserted with the first mem wdata 127:0 out Memory write data data output pixel of a line. mem addr 31:0 out Memory read / write data address Generic memory interface mem addr val out Memory request valid high mem addr rdy in Ready to accept high The memory interface is a generic single-ported 128-bit read/write type memory request that may be connected to a wide variety of memories and memory (handshake signal) controllers. mem rdata 127:0 in Memory read data data Each memory request is sent using the valid-ready protocol. A request is mem rdata val in Memory read data high transferred on a rising clock edge when mem addr val and valid mem addr rdy are asserted high. If the request is a write then the flag mem rw is asserted low. For a memory read, then the mem rw flag is asserted high. The mem addr signal is common to both read and write requests. 3 Assuming frame-repeat mode is enabled Copyright 2017 www.zipcores.com Download this IP Core Page 2 of 7