LVDS SERDES High-speed LVDS (SERDES) Transceiver Rev. 1.4 Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core Separate LVDS Transmitter / Receiver (SERDES) pair Up to 8 serial LVDS data lanes + LVDS clock Fully configurable clocking (duty cycle + skew) Generic parallel data width up to 128 bits wide Generic parallel-to-serial mux ratio up to 16:1 Data rates of up to 1 Gbits per lane Integrated asynchronous FIFOs with underflow / overflow detection. Bitwise data alignment at the receiver No receiver source clock required Compatible with a wide range of industry standard protocols including: Channel-Link, Camera-Link, FPD-Link, FlatLink, MIPI etc. Robust and simple to implement using cheap twisted pair cable (e.g. Cat 5E Ethernet) Applications High bandwidth SERDES interfaces Serialization of wide buses e.g. virtual ribbon cable Direct replacement for many commercial LVDS ICs Transport of digital data (e.g. video) over distances of 10m+ Generic Parameters Generic name Description Type Valid range dw Parallel data width integer 2 dw 128 ratio Parallel-to-serial integer 2 ratio 16 multiplexer ratio duty Transmitter clock duty integer 0 < duty < ratio cycle setting skew Transmitter clock integer 0 skew ratio skew setting lanes Number of serial data integer dw / ratio lanes (8 max) Figure 1: LVDS (SERDES) Transmitter (a) and Receiver (b) direction Serialization/De integer 0: forward architectures serialization direction 1: backward polarity Receiver clock integer 0: -ve edge sampling edge 1: +ve edge Copyright 2015 www.zipcores.com Download this VHDL Core Page 1 of 6LVDS SERDES High-speed LVDS (SERDES) Transceiver Rev. 1.4 Pin-out Description General Description LVDS TRANSMITTER The LVDS SERDES IP Core is a high-speed LVDS Transmitter/Receiver pair suitable for a wide range of serial interface applications. The design Pin name I/O Description Active state is comprised of an independent transmitter and receiver that may be used sys clk in System clock rising edge separately, or together as a single transceiver. (Synchronous with parallel input data) The transceiver can accept parallel data widths of up to 128-bits and features a user-defined multiplexer ratio. By modifying the generic ser clk in Serial clock rising edge parameters, dw, ratio, duty, skew, lanes and direction, the transceiver can (sys clk multiplied by the be made compatible with a wide range of third-party LVDS devices such mux ratio) as those from National Semiconductor, TI, Thine and Maxim. reset in Asynchronous reset low In total, the transceiver can support up to 8 serial data lanes - each data underflow out Error flag: indicates high lane typically handling rates of between 500 Mbits/s and 1Gbits/s. The starvation of data if: (sticky until maximum data rate attained will be dependent on a wide range of factors (sys clk x ratio < ser clk) reset) such as: cable type, cable length, board layout, and the specification of the LVDS buffers. As a general rule, data rates of 350 Mbits/s per lane overflow out Error flag: indicates a high can be easily achieved on even the most basic FPGA platforms. surplus of data if: (sticky until (sys clk x ratio > ser clk) reset) In addition to the 8 data lanes, a single clock lane is provided for rst flags in Reset error flags high synchronizing the data between the transmitter and receiver. Figure 1 shows the basic architecture of the transmitter and receiver pair. The datain dw-1:0 in Parallel input data data following sections explain the individual IP Cores in more detail. datain val in Parallel input data valid high txN p (max 8) out Positive Tx strobe serial LVDS LVDS Transmitter data lane N txN n (max 8) out Negative Tx strobe serial LVDS The transmitter is responsible for serializing the parallel input data into data lane N separate data lanes. The input data is partitioned into N groups, where tx clk p out Positive Tx clock strobe LVDS the width of each group is defined by the generic parameter ratio. As an example, consider a parallel data width of 21-bits and a mux ratio of 7. tx clk n out Negative Tx clock strobe LVDS The resulting architecture would have 3 data lanes in an arrangement like that shown in Figure 2 below: LVDS RECEIVER Pin name I/O Description Active state sys clk out System clock rising edge (Synchronous with parallel output data) reset in Asynchronous reset low underflow out Error flag: indicates high starvation of data if: (sticky until Figure 2: Multiplexer arrangement for a data width of 21-bits (sys clk x ratio < ser clk) reset) and a ratio of 7 overflow out Error flag: indicates a high surplus of data if: (sticky until (sys clk x ratio > ser clk) reset) The output order of the bits within each multiplexer is controlled by the generic parameter direction. With direction set to 1 then the serial bits rst flags in Reset error flags high are multiplexed in the order 0, 1, 2, etc. When direction is 0 then the bit slip in Bit shift strobe rising edge order is reversed. The direction parameter is provided for compatibility (Causes parallel data with various third party SERDES solutions. output word to be barrel- shifted by one bit. Used to The transmitter requires two separate clocks for correct operation. The align output data) signal sys clk is a system clock that is synchronous with the input data. The signal ser clk is the serial clock. The system clock and serial clock dataout dw-1:0 out Parallel output data data do not need to be phase-aligned, but the serial clock must be an exact integer multiple of the system clock with the relationship: dataout val out Parallel output data valid high rxN p (max 8) in Positive Rx strobe serial LVDS data lane N ser clk=sys clkratio rxN n (max 8) in Negative Rx strobe serial LVDS data lane N After system reset, transmission of data begins on a rising clock-edge of rx clk p in Positive Rx clock strobe LVDS sys clk when datain val is asserted high. The serialization process then begins with parallel data words being read on consecutive system clock rx clk n in Negative Rx clock strobe LVDS cycles. Copyright 2015 www.zipcores.com Download this VHDL Core Page 2 of 6