DDS Direct Digital Synthesizer / Periodic waveform generator Rev. 1.5 Key Design Features Block Diagram Synthesizable, technology independent IP Core fro FPGA, seed ASIC and SoC 32 Supplied as human readable VHDL (or Verilog) source code squ out 32-BIT LFSR 16 SQUARE/RAMP DITHER 16-bit signed output data samples GENERATOR SEQUENCE saw out 16 reset 32-bit phase accumulator (tuning word) 16 32-bit phase shift feature en O 32-BIT PHASE QUANTIZE ACCUMULATOR 32 + 32 PHASE 16 clk Phase resolution of 2 / 2 16 32 Frequency resolution of F / 2 (F = sample frequency) S S 32 32 (8-BIT OPTION) (12-BIT OPTION) Phase dithering option for improved SFDR lutsize 8, 12 or 16 (16-BIT OPTION) sin out 16 100 dB SNR and > 110 dB SFDR (with phase dithering SIN / COS enabled) 1/4-WAVE LUT cos out 16 Simultaneous SIN, COS, square and sawtooth outputs Optimized quarter-wave LUT for reduced area footprint Figure 1: Direct Digital Synthesizer architecture 1 Sample rates of 350 MHz+ Generic Parameters Applications Generic name Description Type Valid range Digital oscillators and phase-locked loops dithering Enable phase boolean TRUE/FALSE dithering Digital modulation/demodulation Digital up/down converters and mixers lutsize Use an 8,12 or 16-bit integer 8, 16 or 12 Look-up table Generation of quadrature (complex) signals (Effective size) Versatile waveform generation 32 seed Seed for random std logic 0 < seed < 2 number generator vector Pin-out Description General Description Pin name I/O Description Active state clk in Sample clock rising edge 2 The DDS IP Core is a high-precision Direct Digital Synthesizer used for reset in Asynchronous reset low the generation of periodic waveforms. On each rising-edge of the sample clock and when the clock-enable is high, the phase in the phase- en in clock enable high accumulator is incremented by the value phase inc. This phase is phase inc 31:0 in Phase increment as an data quantized to 16-bits and passed as an address to a look-up table which unsigned 32-bit number converts the phase into a waveform. phase shift 31:0 in Phase shift as an unsigned data To save resources, the look-up table is implemented as a quarter sine 32-bit number wave (16384 x 15-bit samples). These samples are manipulated to sin out 15:0 out Sine wave output data generate 65536 x 16-bit samples over the range 0 to 2Pi. By setting the (16-bit signed number) generic parameter lutsize to 12 or 8, the size of the LUT can be reduced further to (1024 x 11-bit) or (64 x 7-bit) if required. The general cos out 15:0 out Cosine wave output data architecture of the DDS circuit is shown in Figure 1 above. (16-bit signed number) In addition to the quadrature outputs sin out and cos out, the DDS also squ out 15:0 out Square wave output data provides square wave and sawtooth outputs: squ out and saw out. All (16-bit signed number) output values are 16-bit signed numbers. saw out 15:0 out Sawtooth wave output data (16-bit signed number) 1 Xilinx 7-series FPGAs used as a benchmark 2 Also known as a Numerically Controlled Oscillator (NCO) Copyright 2019 www.zipcores.com Download this IP Core Page 1 of 5 phase inc phase shiftDDS Direct Digital Synthesizer / Periodic waveform generator Rev. 1.5 Phase increment The random number used for phase dithering is generated using a Linear Feedback Shift Register (LFSR) of order 32. The LFSR is free running and generates a random bit every sample clock in accordance with the The frequency of the DDS output waveform is controlled by the phase inc polynomial: signal on a clock-by-clock basis. A change in the phase increment during normal circuit operation will affect a change in the output waveform 5 32 7 5 3 2 1 0 sample clocks later. The phase increment may be calculated using the x x x x x x x formula: The user may choose any number (other than zero) as an initial seed for 32 =(F 2 )/ F the random number generator. Different seeds, in some cases, can INC OUT S change the SFDR by around +/- 1dB. Where F is the desired waveform output frequency and F is the OUT S sampling frequency. Note that an integer value of the phase increment Functional Timing must be used. As an example, consider a 100 MHz sample clock with a desired output frequency of 6.197 MHz. The phase increment would be 32 calculated as (6.197 * 2 ) / 100 = 266159123. Figure 2 shows the operation of the DDS immediately after reset. After reset goes high the DDS starts to generate the output waveforms 5 clock The minimum and maximum frequencies DDS can generate are given by cycles later. Asserting the clock-enable low will stall the pipeline. the following formulas: Asserting clock-enable high once again will start waveform output at the next sample point in the waveform. 32 , F =F / 2 F = F / 2 MAX S MIN S As an example, a 100 MHz sample clock would allow a minimum DDS frequency of 0.0233 Hz. This is sometimes called the frequency resolution of the DDS. Conversely, the maximum frequency the DDS can generate is given by the Nyquist-Shannon sampling theorem (Fs / 2). Phase shift The relative phase of the DDS output waveform may be controlled by the phase shift input. This input takes the form of a 32-bit unsigned value that is added to the phase accumulator. To implement a phase shift, then the phase shift input should be asserted for 1 clock cycle. At all other times then the phase shift must be set to zero. The phase shift in degrees is calculated using the following formula: 32 = / 3602 SHIFT For example, to implement a phase shift of 45 in the output waveform 32 then the phase shift input would be calculated as (45/360)*2 or 0x20000000 in hex. This value of phase shift should be asserted for one clock cycle then reset to 0x00000000. Phase dithering The process of phase quantization introduces noise on the phase signal and it produces unwanted spurious spectral components in the DDS output signal (referred to as spurs). The difference between the carrier level and the maximum level of spurs is called the Spurious Free Dynamic Range (SFDR). The DDS component alleviates this problem by adding a random number to the LSBs of the 32-bit phase accumulator before quantization. This has the effect of spreading the spurs throughout the available bandwidth while preventing spurs at the same harmonic frequencies reinforcing each other. With phase dithering enabled, an improvement of around 10 to 20 dB in SFDR may be achieved. Figure 2: DDS operation after reset Copyright 2019 www.zipcores.com Download this IP Core Page 2 of 5 clk reset en phase inc 0x40000000 sin out 0x0003 0x7FFF 0x0000 0x8001 0x0000 0x7FFF cos out 0x7FFF 0x0000 0x8001 0x0000 0x7FFF 0xFFFD squ out 0x8000 0x7FFF 0x8000 saw out 0x0001 0x4000 0x8000 0xC000 0x0000 0x4001