SPI MASTER SPI Master Serial Interface Controller Rev. 1.3 Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, reset ASIC and SoC Supplied as human readable VHDL (or Verilog) source code mast sel mast inst SPI serial-bus compliant PAD mast data sclk Supports up to 16 slave devices mast val PAD mast rdy Intuitive command interface featuring a simple valid-ready ss 0 handshake protocol clk PAD ss 1 Input/output FIFOs permit queuing of sequential SPI requests WRITE FIFO SPI MASTER and corresponding read data CONTROLLER READ FIFO slv sel PAD Architecture allows sustained 8-bit read/write operations ss 15 slv inst Configurable serial clock frequency PAD slv data mosi Configurable clock polarity setting (CPOL) slv val PAD slv rdy miso Configurable clock phase setting (CPHA) Capable of full-duplex or half-duplex operation 1 Data rates of up to 40 Mbps+ Figure 1: SPI Master Interface Controller architecture Applications Pin-out Description Driving SPI slave devices Pin name I/O Description Active state Inter-chip board-level communications clk in Synchronous clock rising edge Robust communication at higher data rates than other serial reset in Asynchronous reset low protocols such as I2C, UART and USB 1.0 mast sel 3:0 in Slave device selection data (0 to 15) Generic Parameters mast inst 1:0 in Master instruction data mast data 7:0 in Master data to be data serialized Generic name Description Type Valid range mast val in Master instruction valid high t period Serial clock period (in integer 5 system clock cycles) mast rdy out Master ready handshake high cpol Clock polarity integer 0, 1 sclk out SPI serial clock rising or falling 2 (As per SPI edge specification) ss 15:0 out SPI slave select low cpha Clock phase integer 0, 1 (One hot decode) (As per SPI mosi out SPI Master out / Slave in data specification) miso in SPI Master in / Slave out data wfifo depth Master instruction integer 2 write FIFO depth slv sel 3:0 out Slave device id data wfifo depth log2 Master instruction integer log2 slv inst 1:0 out Slave instruction data write FIFO depth log2 (wfifo depth) slv data 7:0 out Slave data received from data rfifo depth Slave read data FIFO integer 2 slave device depth slv val out Slave data valid high rfifo depth log2 Slave read data FIFO integer log2 depth log2 (rfifo depth) slv rdy in Slave ready handshake high 1 Maximum attainable data rate will generally be determined by the 2 Note that the serial clock characteristics are dependent on the CPOL slave SPI device and the physical characteristics of the bus and CPHA settings. See the SPI specification for more details Copyright 2017 www.zipcores.com Download this VHDL Core Page 1 of 5 FIFO stage n FIFO stage 0 FIFO stage 1 FIFO stage 1 FIFO stage 0 FIFO stage nSPI MASTER SPI Master Serial Interface Controller Rev. 1.3 MASTER INSTRUCTION INPUT FORMAT General Description mast inst 3:0 mast data 7:0 Description 00 7:0 : Write data SPI WRITE The SPI MASTER IP Core is an SPI compliant serial interface controller capable of driving up to 16 different slave devices in full-duplex operation. Write 8-bits serially on the SPI The controller receives data and instructions via the master instruction bus. Ignore the read data bits interface. These instructions are then processed by the controller core in order to generate the appropriate signals on the SPI bus. The serial slave (Half-duplex operation) data on the SPI bus is also captured by the controller and de-serialized for presentation at the slave read data port. 01 7:0 : X Don t care SPI READ The SPI master controller is comprised of three main blocks as described Read 8-bits serially on the SPI by Figure 1. These blocks are the master instruction write FIFO, the SPI bus. Write data is don t care. controller core and the slave read-data output FIFO. (Half-duplex operation) The serial clock-period is determined by the generic parameter t period. 10 7:0 : Write data SPI READ/WRITE This parameter specifies the sclk period in system clock cycles. As an example, if the system clock clk is running at 130 MHz and a serial clock Read and write 8-bits serially frequency of 10 MHz is required, a value of t period = 13 should be on the SPI bus. specified. In addition, the generic parameters cpol and cpha permit the clock polarity and phase characteristics to be specified as per the SPI (Full-duplex operation) specification. The table below shows a brief summary of these settings. 11 7:0 : Don t care NULL CPOL CPHA Description Dummy instruction. 0 0 Serial clock default state logic 0 (May be used to force the Data sampled on rising-edge of serial clock slave select signal inactive Data changes on falling-edge of serial clock between sequential SPI transfers) 0 1 Serial clock default state logic 0 Data sampled on falling-edge of serial clock Data changes on rising-edge of serial clock As an example, to write two consecutive bytes followed by two 1 0 Serial clock default state logic 1 consecutive reads from the same slave device with the slave select signal Data sampled on falling-edge of serial clock forced inactive-high in between, the instructions 00, 00, 11, 01, 01 Data changes on rising-edge of serial clock would be sent. 1 1 Serial clock default state logic 1 Data sampled on rising-edge of serial clock Of course, the exact sequence of instructions required will depend on the Data changes on falling-edge of serial clock functionality of the slave device that is to be accessed. For this reason, there is no restriction in the ordering of instructions that may be sent to to the SPI master controller. Master Write FIFO SPI Master Controller Core Instructions to the SPI master controller are sent via an input FIFO whose depth is determined by the generic parameter wfifo depth. The write The master controller is a state-machine that accepts instructions from FIFO interface operates in accordance with a simple valid/ready pipeline the write FIFO and generates the appropriate signals on the SPI bus. protocol meaning that instructions and data are written to the FIFO on the 3 Immediately after an asynchronous reset of the core, the state machine rising edge of clk when mast val is high and mast rdy is high starts in the reset state with the slave select lines ss inactive high. On receipt of the first valid instruction, the state machine will take control of The write FIFO may be used to queue up a sequence of commands and the bus and drive the sclk, ss and mosi lines in response to the received data while current commands are being processed on the bus. As soon instructions and data. If the instruction is a read operation, the controller as the write FIFO becomes full then the FIFO will disable the mast rdy will also sample the input serial data on the miso pin. signal signifying that further requests are not possible. The default state of the serial clock and the edges in which the serial data Likewise, the mast rdy signal will also be disabled if the slave read-data are sampled and changed is dependent on the cpol and cpha settings as FIFO becomes full. In both situations, no further commands will be described earlier. accepted by the SPI controller until the FIFOs have emptied. The instructions to the SPI controller are very intuitive and follow the Slave Read FIFO exact sequence of commands that the user wishes to appear on the SPI bus. The following table outlines the set of commands accepted by the controller via the master write FIFO. For every master instruction received by the controller, the controller also sends a copy of the original instruction plus the slave read data (if applicable) to the slave read FIFO. In the case that the originating instruction was a slave write then the slave read data contains a copy of the original master data. The following table gives a brief summary of the instruction format. 3 See Zipcores application note: app note zc001.pdf for more examples of the valid/ready protocol and it s implementation Copyright 2017 www.zipcores.com Download this VHDL Core Page 2 of 5