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PIPE SQRT Pipelined Square-root with generic width Rev. 1.2 Key Design Features Block Diagram Synthesizable, technology independent VHDL Core Function f(x) = x Input and output values as unsigned integers Configurable data width Unsigned N-bit input generates a result with N/2 integer bits and N/2 fraction bits Figure 1: Pipelined Square-root Architecture (N/2) Precision to within 1/2 General Description High-speed fully pipelined architecture with configurable number of register stages for area/speed trade off PIPE SQRT (Figure 1) is a pipelined square-root with configurable data width. The design is fully scalable and modular permitting the user to One output result per clock-cycle (i.e. pipelined operation) specify large bit widths without compromising maximum attainable clock speed. Capable of clock speeds of 250MHz+ on even basic FPGA platforms The function accepts input values as unsigned integers whose width is specified by the parameter dw. The output result also contains dw bits and is separated into an integer part and fractional part each of dw/2 bits Applications wide. Figure 2 below shows an example calculation using 8-bit arithmetic. The Basic building block in digital processing functions input 00111101 (61) would result in an output of: 0111.1101 i.e. an integer part of 7 and a fractional part of 0.8125. 1 Square root of integers and fixed-point numbers Magnitude calculation of complex signals in digital communications systems Pin-out Description Pin name I/O Description Active state clk in Synchronous clock rising edge Figure 2: 8-bit square-root example en in Clock enable high Values are sampled on the rising clock-edge of clk when en is high. The a in dw-1:0 in Unsigned input number data number of register stages in the pipeline may be modified in order to trade sqrt dw -1:0 out Unsigned output square data off maximum speed against the total resource used. The overall pipeline root latency of the square root function is given by the following formula: Generic Parameters Latency=(dw1)/ reg stages The total latency should be rounded up to the nearest whole number. For Generic name Description Type Valid range instance, when the generic parameter dw = 16 and reg stages is set to 3, dw Input data width integer 2 then the function has a fixed cycle latency of 16-1/3 = 5 clock cycles. In (dw = even) other words, the result of the square-root will take 5 clock cycles to appear at the output. reg stages Number of pipeline integer 1 Note that while the latency may change depending on the reg stages register stages dw setting, the throughput is always maintained at one output result per clock. 1 For fixed-point numbers then inputs must be pre-scaled by a power of 2 and the result wire-shifted. E.g. the computation 0.2 could be done as 51 with a shift right of 4 Copyright 2011 www.zipcores.com Download this VHDL Core Page 1 of 3PIPE SQRT Pipelined Square-root with generic width Rev. 1.2 Functional Timing Figure 3 demonstrates the calculation of 57728. In this example, the generic parameter dw has been set to 16 and reg stages is set to 5. Note that the result has a latency of 3 clock cycles. The result is given as 61509, which as an 8.8-bit value represents the number 240.27. Figure 3: Calculation of the square-root of 57728 with a data width of 16-bits Figure 4: Plot of test results for function: f(x) = x Synthesis Source File Description The source files required for synthesis and the design hierarchy is shown All source files are provided as text files coded in VHDL. The following below: table gives a brief description of each file. pipe sqrt.vhd Source file Description pipe sqrt subsquare.vhd pipe sqrt subsquare.vhd Subtract square block pipe sqrt.vhd Top-level block The VHDL core is designed to be technology independent. However, as pipe sqrt bench.vhd Top-level test bench a benchmark, synthesis results have been provided for the Xilinx Virtex 5 and the Altera Stratix III series of FPGA devices. The lowest and highest speed grade devices have been chosen in both cases for comparison. Functional Testing Note that the generic parameter reg stages will have a signification effect on the speed and area of the synthesized design. For the fastest possible design, the generic parameter reg stages should be set to 1. For the An example VHDL testbench is provided for use in a suitable VHDL smallest design, then reg stages should be set to equal the data width, simulator. The compilation order of the source code is as follows: dw. Trial synthesis results are shown with the generic parameters set to dw = 1. pipe sqrt subsquare.vhd 16 and reg stages = 1. Resource usage is specified after Place and 2. pipe sqrt.vhd Route. 3. pipe sqrt bench.vhd VIRTEX 5 The VHDL testbench instantiates the square-root component and the user may modify the generic parameters as required. The simulation must be Resource type Quantity used run for at least 2 ms during which time the square root function will be Slice register 329 driven with a randomized sequence of input values. The test terminates automatically. Slice LUT 49 Block RAM 0 The simulation generates two text files called: pipe sqrt in.txt and pipe sqrt out.txt. These files respectively contain the input and output DSP48 15 data samples captured at the interfaces during the test. Clock frequency (worst case) 161 MHz Figure 4 shows the results of the square-root function for the first 1000 Clock frequency (best case) 264 MHz natural numbers with the generic parameter dw = 16. Copyright 2011 www.zipcores.com Download this VHDL Core Page 2 of 3