74VHCT00AFT CMOS Digital Integrated Circuits Silicon Monolithic 74VHCT00AFT74VHCT00AFT74VHCT00AFT74VHCT00AFT 1. 1. Functional DescriptionFunctional Description 1. 1. Functional DescriptionFunctional Description Quad 2-Input NAND Gate 2. 2. 2. 2. GeneralGeneralGeneralGeneral The 74VHCT00AFT is an advanced high speed CMOS 2-INPUT NAND GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3 V to 5 V system. Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, hot board insertion, etc. Note: V = 0 V CC 3. 3. FeaturesFeatures 3. 3. FeaturesFeatures (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature range: T = -40 to 125 opr (3) High speed: t = 5.0 ns (typ.) at V = 5.0 V pd CC (4) Low power dissipation: I = 2.0 A (max) at T = 25 CC a (5) Compatible with TTL outputs: V = 0.8 V (max) IL V = 2.0 V (min) IH (6) Power-down protection is provided on all inputs and outputs. (7) Balanced propagation delays: t t PLH PHL (8) Low noise: V = 0.8 V (max) OLP (9) Pin and function compatible with the 74 series (ACT/HCT/AHCT etc.) 00 type. Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales representative. 4. 4. 4. 4. PackagingPackagingPackagingPackaging TSSOP14B Start of commercial production 2013-06 2017 Toshiba Corporation 2017-02-22 1 Rev.4.074VHCT00AFT 5. 5. 5. 5. Pin AssignmentPin AssignmentPin AssignmentPin Assignment 6. 6. 6. 6. MarkingMarkingMarkingMarking 7. 7. IEC Logic SymbolIEC Logic Symbol 7. 7. IEC Logic SymbolIEC Logic Symbol 2017 Toshiba Corporation 2017-02-22 2 Rev.4.0