STG5223 Low voltage 0.5 dual SPDT switch with break-before-make Features Ultra low power dissipation: I = 0.2 A (max.) at T = 85 C CC A Low ON resistance: R =0.50 (max. T =25C) at ON A V =4.3 V CC R =0.55 (max. T =25C) at ON A V =3.6 V CC QFN10 R =0.55 (max. T =25C) at ON A (1.8x1.4 mm) V =3.0 V CC Wide operating voltage range: exists between the two ports) when nIN is held V (opr) = 1.65 V to 4.3 V single supply CC low. The switches nS2 are ON (connected to 5 V tolerant and 1.8 V compatible threshold on common ports Dn) when the nIN input is held low digital control input at V = 1.65 to 4.3 V CC and OFF (high impedance state exists between Latch-up performance exceeds 300 mA the two ports) when IN is held high. Additional key (JESD 17) features are fast switching speed, break-before- make delay time and ultra low power ESD performance: consumption. All inputs and outputs are equipped HBM > 2 kV (MIL STD 883 method 3015) with protection circuits against static discharge, giving them ESD immunity and transient excess Description voltage immunity. The STG5223 is a high-speed CMOS dual analog SPDT (single pole dual throw) switch or dual 2:1 multiplexer/demultiplexer bus switch fabricated in 2 silicon gate C MOS technology. It is designed to operate from 1.65 to 4.3 V, making this device ideal for portable applications. It offers very low ON resistance (<0.5 ) at V = 3.0 V. The nIN inputs are provided to CC control the switches. The switches nS1 are ON (connected to common ports Dn) when the nIN input is held high and OFF (high impedance state Table 1. Device summary Order code Package Packaging STG5223QTR QFN10 (1.8 x 1.4 mm) Tape and reel May 2009 Doc ID 14312 Rev 3 1/19 www.st.com 19 Contents STG5223 Contents 1 Pin settings 3 1.1 Pin connection 3 1.2 Pin description 3 2 Input equivalent circuit and truth table 4 3 Maximum rating . 5 3.1 Recommended operating conditions . 6 4 Electrical characteristics . 7 5 Test circuit 10 6 Package mechanical data 14 7 Revision history . 18 2/19 Doc ID 14312 Rev 3