M74HC597 8 BIT LATCH/SHIFT REGISTER HIGH SPEED : f = 50 MHz (TYP.) at V = 6V MAX CC LOW POWER DISSIPATION: I =4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: t t ORDER CODES PLH PHL WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T & R V (OPR) = 2V to 6V CC DIP M74HC597B1R PIN AND FUNCTION COMPATIBLE WITH SOP M74HC597M1R M74HC597RM13TR 74 SERIES 597 TSSOP M74HC597TTR DESCRIPTION The M74HC597 is an high speed CMOS 8 BIT register and shift register have positive edge PIPO SHIFT REGISTER fabricated with silicon triggered clocks. The shift register also has direct 2 gate C MOS technology. load (from storage) and clear inputs. This devices comes in a 16-pin package and All inputs are equipped with protection circuits consist of an 8-bit storage latch feeding a parallel against static discharge and transient excess in, serial out 8-bit shift register. Both the storage voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/14M74HC597 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 9 QH Serial Data Outputs Asynchronous Reset 10 SCLR Input (Active LOW) Shift Clock Input (LOW to 11 SCK HIGH Edge-triggered) Storage Clock Input (LOW 12 RCK to HIGH Edge-triggered) Parallel Data Input (Active 13 SLOAD Low) 10 SI Serial Data Input 15, 1, 2, 3, 4, A to H Parallel Data Inputs 5, 6, 7 8 GND Ground (0V) 16 Vcc Positive Supply Voltage TRUTH TABLE INPUTS OUTPUT SI SCK SCLR SLOAD RCK X X L H X S.R. IS CLEARED TO X X H L X INPUT REGISTER DATA IS STORED INTO S.R. FIRST STAGE OF S.R. BECOMES OTHER STAGES LHHX STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY FIRST STAGE OF S.R. BECOMES OTHER STAGES HHHX STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY X H H X STATE OF S.R. IS NOT CHANGED INPUT DATA ON A ~ H LINE IS STORED INTO INPUT REG- XXXX ISTER XXXX STORAGE REGISTER STATE IS NOT CHANGED X : Dont Care 2/14