M74HC148 8 TO 3 LINE PRIORITY ENCODER HIGH SPEED: t = 16ns (TYP.) at V = 6V PD CC LOW POWER DISSIPATION: I = 4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: t t ORDER CODES PLH PHL WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T & R V (OPR) = 2V to 6V CC DIP M74HC148B1R PIN AND FUNCTION COMPATIBLE WITH SOP M74HC148M1R M74HC148RM13TR 74 SERIES 148 TSSOP M74HC148TTR DESCRIPTION The M74HC148 is an high speed CMOS 8 TO 3 has been provided to allow octal expansion LINE PRIORITY ENCODER fabricated with without the need for external circuitry. Data inputs 2 silicon gate C MOS technology. are active at the low logic level. The M74HC148 encodes eight data lines to All inputs are equipped with protection circuits three-line (4-2-1) binary (octal). Cascading against static discharge and transient excess circuitry (enable input EI and enable output EO) voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11 Obsolete Product(s) - Obsolete Product(s)M74HC148 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 9, 7, 6 A to A Data Outputs 0 2 10, 11, 12, 0 to 7 Data Inputs 13, 1, 2, 3, 4 15 EO Enable Output 5 EI Enable Input 14 GS Priority Flag Output 8 GND Ground (0V) 16 V Positive Supply Voltage CC TRUTH TABLE INPUTS OUTPUTS E1 01234567 A2 A1 A0 GS E0 HXXXXXXXX H H H H H L HHHHHHHHHH HH L L XXXXXXX L L L L L H L XXXXXX L H L L H L H L XXXXX L H H L H L L H L XXXX L H H H L H H L H L X X X L HHHHH L L L H L X X L HHHHHH L H L H L X L HHHHHHHH L L H L L HHHHHHHHH H L H X : Dont Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11 Obsolete Product(s) - Obsolete Product(s)