M48Z129V 3.3 V, 1 Mbit (128 Kb x 8) ZEROPOWER SRAM Not recommended for new design Features Integrated, ultra low power SRAM, power-fail control circuit, and battery Conventional SRAM operation unlimited WRITE cycles 10 years of data retention in the absence of power Microprocessor power-on reset (reset valid 32 even during battery backup mode) 1 Battery low pin - provides warning of battery end-of-life Automatic power-fail chip deselect and WRITE protection PMDIP32 module WRITE protect voltages V = 3.0 to 3.6 V 2.7 V V 3.0 V CC PFD (V = power-fail deselect voltage) PFD Self-contained battery in the CAPHAT DIP package Pin and function compatible with JEDEC standard 128 K x 8 SRAMs RoHS compliant Lead-free second level interconnect September 2011 Doc ID 5716 Rev 8 1/20 This is information on a product still in production but not recommended for new designs. www.st.com 1 Obsolete Product(s) - Obsolete Product(s)Contents M48Z129V Contents 1 Description . 5 2 Operation modes 7 2.1 READ mode 7 2.2 WRITE mode . 9 2.3 Data retention mode . 10 2.4 V noise and negative going transients . 11 CC 3 Maximum ratings . 12 4 DC and AC parameters 13 5 Package mechanical data 16 6 Part numbering 17 7 Environmental information . 18 8 Revision history . 19 2/20 Doc ID 5716 Rev 8 Obsolete Product(s) - Obsolete Product(s)