AS21P2TLR Low voltage 0.5 max dual single-pole double-throw analog switch with break-before-make Datasheet - production data Description The AS21P2TLR is a high-speed CMOS single- pole double-throw (SPDT) analog switch or dual 2:1 multiplexer/demultiplexer bus switch fabricated using silicon gate CMOS technology. Designed to operate from 1.65 to 4.3 V, this device is ideal for portable applications. (1.8 x 1.4 mm) It offers very low ON resistance (R <0.5 ) at ON V = 3.6 V. The nIN inputs are provided to CC control the independent channel switches nS1 and nS2. The switches nS1 are ON (connected to common ports Dn) when the nIN input is held high and OFF (state of high impedance exists between Features the two ports) when nIN is held low. The switches nS2 are ON (connected to common ports Dn) Ultra low power dissipation: I = 0.2 A (max.) CC when the nIN input is held low and OFF (state of at T = 85 C A high impedance exists between the two ports) Low ON resistance V = 0 V: IN when IN is held high. Additional key features are R = 0.50 (max. T = 25 C) at fast switching speed, break-before-make delay ON A V = 4.3 V time and ultralow power consumption. All inputs CC and outputs are equipped with protection circuits R = 0.50 (max. T = 25 C) at ON A against static discharge, giving them ESD and V = 3.6 V CC excess transient voltage immunity. Wide operating voltage range: V (OPR) = 1.65 to 4.3 V single supply CC 4.3 V tolerant and 1.8 V compatible threshold on digital control input at V = 2.3 to 4.3 V CC Latch-up performance exceeds 300 mA (JESD 17) ESD performance: HMB > 2 kV (MIL STD 883 method 3015) Table 1. Device summary Order code Package Packing AS21P2TLRQ QFN10L (1.8 x 1.4 mm) Tape and reel March 2014 DocID026024 Rev 1 1/22 This is information on a product in full production. www.st.comContents AS21P2TLR Contents 1 Pin settings 3 1.1 Pin connection 3 1.2 Pin description 4 2 Input equivalent circuit and truth table 5 3 Maximum rating . 6 4 Electrical characteristics . 7 5 Test circuit 10 6 Package mechanical data 16 7 Revision history . 21 2/22 DocID026024 Rev 1