SX1308 WIRELESS & SENSING PRODUCTS Datasheet SX1308 I/Q DDR - LoRa DDR - LoRa DDR - LoRa Tx/Rx I/Q 8x LoRa I/Q (Tx/Rx) I/Q (G)FSK MCU SPI Packet timestamp (GPS) (G)FSK/LoRa handler General Description Key Product Features The SX1308 digital baseband chip is a massive Up to -139 dBm sensitivity with SX1257 digital signal processing engine specifically or SX1255 Tx/Rx front-end designed to offer breakthrough gateway 70 dB CW interferer rejection at capabilities in the ISM bands worldwide. It 1 MHz offset integrates the LoRa concentrator IP. Able to operate with negative SNR CCR up to 9 dB The LoRa concentrator is a multi-channel high Emulates 49x LoRa demodulators and 1x performance transmitter/receiver designed to (G)FSK demodulator simultaneously receive several LoRa packets Dual digital Tx & Rx radio front-end using random spreading factors on random interfaces channels. Its goal is to enable robust 10 programmable parallel demodulation connection between a central wireless data paths concentrator and a massive amount of Dynamic data-rate adaptation (ADR) wireless end-points spread over a very wide True antenna diversity or simultaneous range of distances. dual-band operation The SX1308 is targeted at smart metering fixed networks and Internet of Things applications. Applications Smart Metering Security Sensors Network Agricultural Monitoring Internet of Things (IoT) Ordering Information Part Number Conditioning SX1308IMLTRT Tape & Reel 3,000 parts per reel Pb-free, Halogen free, RoHS/WEEE compliant product V1.2 June 2017 www.semtech.com 1 Packet handler ControlSX1308 WIRELESS & SENSING PRODUCTS Datasheet Contents 1 PIN CONFIGURATION .................................................................................................................. 4 1.1 Pins Placement and Circuit Marking ........................................................................................... 4 1.2 Pins Description .......................................................................................................................... 5 2 ELECTRICAL CHARACTERISTICS ................................................................................................... 7 2.1 Absolute Maximum Ratings ........................................................................................................ 7 2.2 Constraints on External ............................................................................................................... 7 2.3 Operating Conditions .................................................................................................................. 7 2.4 Electrical Specifications ............................................................................................................... 8 2.5 Timing Specifications .................................................................................................................. 8 3 CIRCUIT OPERATION ................................................................................................................... 9 3.1 General Presentation .................................................................................................................. 9 3.2 Power-On .................................................................................................................................... 9 3.2.1 Power-Up Sequence ................................................................................................................ 9 3.2.2 Setting the Circuit is Low-Power Mode .................................................................................. 9 3.3 Clocking ..................................................................................................................................... 10 3.4 SPI Interface .............................................................................................................................. 11 3.5 Rx I/Q Interface ......................................................................................................................... 12 3.5.1 I/Q Generated on Clock Rising Edge ..................................................................................... 12 3.5.2 I/Q Generated on Clock Falling Edge .................................................................................... 12 3.6 RX Mode Block Diagram, Reception Paths Characteristics ....................................................... 13 3.6.1 Block Diagram ....................................................................................................................... 13 3.6.2 Reception Paths Characteristics ............................................................................................ 14 3.7 Packet Engine and Data Buffers ................................................................................................ 15 3.7.1 Receiver Packet Engine ......................................................................................................... 15 3.7.2 Transmitter Packet Engine .................................................................................................... 17 3.8 Receiver IF Frequencies Configuration ..................................................................................... 19 3.8.1 Configuration Using 2 x SX1257 Radios ................................................................................ 19 3.8.2 Two SX1255: 433 MHz Band ................................................................................................. 21 3.8.3 One SX1257 and one SX1255 ................................................................................................ 21 3.9 Connection to RF Front End ...................................................................................................... 22 3.9.1 Connection to Semtech SX1255 or SX1257 Components ..................................................... 22 3.9.2 SX1308 RX Operation Using a Third Party RF Front End ....................................................... 22 3.9.3 Radio Calibration ................................................................................................................... 24 3.9.4 SX1308 Connection to RF Front End for TX Operation ......................................................... 24 3.10 Reference Application ............................................................................................................... 26 3.11 Hardware Abstraction Layer (HAL) ........................................................................................... 27 3.11.1 Introduction .......................................................................................................................... 27 3.11.2 Abstraction Presented to the Gateway Host ........................................................................ 27 4 EXTERNAL COMPONENTS ......................................................................................................... 29 5 PCB LAYOUT CONSIDERATIONS ................................................................................................ 30 6 PACKAGING INFORMATION ...................................................................................................... 32 6.1 Package Outline Drawing .......................................................................................................... 32 6.2 Thermal Impedance of Package ................................................................................................ 32 6.3 Land Pattern Drawing ............................................................................................................... 33 7 REVISION INFORMATION .......................................................................................................... 34 V1.2 June 2017 www.semtech.com 2