Datasheet LVDS Interface LSI 27bit LVDS Dual-out Transmitter BU90T82 General Description Key Specifications 1.62 to 1.98 V The BU90T82 transmitter operates from 10MHz to Supply Voltage Range VDD 1.62 to 3.60 V 174MHz wide clock range, and 27bits data of parallel VDDIO 10 to 174 MHz CMOS level inputs (R/G/B24bits and VSYNC, HSYNC, Operating Frequency -40 to +85 DE) are converted to eight channels of LVDS data Operating Temperature Range stream. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The BU90T82 has low swing mode to be able to expect Package (Typ) (Typ) (Max) further low power and low EMI. SBGA072T070A 7.0mm7.0mm1.2mm Flexible Input/Output mode support various application interfaces. Applications Security camera, Digital camera Tablet Flat Panel Display Features 27bits data of parallel LVCMOS level inputs are Power down mode converted to 4 or 8 channels of LVDS data stream. Clock edge selectable The maximum data rate is 1218Mbps/Lane 6bit/8bit mode selectable Support clock frequency from 10MHz up to 174MHz LVDS output mapping selectable (VESA/JIEDA) Flexible Input/Output mode Support reduced swing LVDS for low EMI 1. Single in / Single LVDS out Support LVDS Outputs pin reverse function 2. Single in / Dual LVDS out Support spread spectrum clock generator input 3. Double edge Single in / Dual LVDS out 4. Single in / Distribution LVDS out Block Diagram LVCMOS Input LVDS Output TCLK1 +/- PLL CLKIN TCLK2 +/- (10MHz - 174MHz) (10MHz - 174MHz) TA1 +/- R1 7:0 8 G1 7:0 8 TB1 +/- B1 7:0 Parallel to Serial 8 LVDS Channel1 Converter HSYNC TC1 +/- Data Mapping VSYNC TD1 +/- DE PWDN OE TA2 +/- RS RF TB2 +/- 6B8B Parallel to Serial MAP LVDS Channel2 Converter MODE TC2 +/- DDRN FLIP PRBS TD2 +/- TEST Figure 1. Block Diagram Product structure : Silicon monolithic integrated circuit This product has no designed protection against radioactive rays . www.rohm.com TSZ02201-0L2L0H500270-1-2 2014 ROHM Co., Ltd. All rights reserved. 1/25 TSZ22111 14 001 06.July.2016 Rev.003DatasheetDatasheet BU90T82 Contents General Description .................................................................................................................................................... 1 Key Specifications ...................................................................................................................................................... 1 Package W(Typ) x D(Typ) x H(Max) .................................................................................................... 1 Applications ................................................................................................................................................................ 1 Features ....................................................................................................................................................................... 1 Block Diagram ............................................................................................................................................................. 1 Figure 1. Block Diagram ......................................................................................................................................... 1 Pin Configuration ........................................................................................................................................................ 4 Figure 2. Pin Configuration .................................................................................................................................... 4 Pin Description............................................................................................................................................................ 5 Absolute Maximum Ratings (Ta = 25C) ................................................................................................................... 6 Recommended Operating Conditions (Ta= -40C to +85C) ................................................................................... 6 DC Characteristics ...................................................................................................................................................... 6 AC Characteristics ...................................................................................................................................................... 7 Figure 3. LVDS Output AC Timing Diagrams ........................................................................................................ 7 Figure 4. LVCMOS Input AC Timing Diagrams ..................................................................................................... 8 Figure 5. LVCMOS Input AC Timing Diagrams (DDRN=L) ................................................................................... 8 LVDS Output AC Timing Diagrams ........................................................................................................................... 9 Figure 6. LVDS Output AC Timing Diagrams ........................................................................................................ 9 Phase Locked Loop Set Time .................................................................................................................................. 9 Figure 7. Phase Locked Loop Set Time ................................................................................................................ 9 Supply Current .......................................................................................................................................................... 10 Figure 8. Gray Scale Pattern, Worst Case Pattern ............................................................................................. 10 LVCMOS Data Inputs Pixel Map Table .................................................................................................................... 11 Output Mode Select on MODE, DDRN Pins ............................................................................................................ 12 Figure 9. Output Mode Select on MODE,DDRN Pins ......................................................................................... 12 DE Input Timing Diagrams ....................................................................................................................................... 12 Figure 10. Dual-out mode DE Input Timing Diagrams (MODE=L) .................................................................... 12 Single-in / Single-out Mode ...................................................................................................................................... 13 Figure 11. Single-in / Single-out Mode ................................................................................................................ 13 Single-in / Dual-out Mode ......................................................................................................................................... 13 Figure 12. Single-in / Dual-out Mode ................................................................................................................... 13 Single-in / Distribution-out Mode ............................................................................................................................ 14 Figure 13. Single-in / Distribution-out Mode ....................................................................................................... 14 Single-in / DDR Dual-out Mode ................................................................................................................................ 14 Figure 14. Single-in / DDR Dual-out Mode .......................................................................................................... 14 LVDS Output Data mapping Table (6B8B = L) .......................................................................................................... 15 Figure 15. 8bit mode LVDS output mapping ....................................................................................................... 15 www.rohm.com TSZ02201-0L2L0H500270-1-2 2014 ROHM Co., Ltd. All rights reserved. 2/25 TSZ22111 15 001 06.July.2016 Rev.003