Datasheet CXPI Transceiver for Automotive BD41001FJ-C General Description Key Specifications BD41001FJ-C can reduce EMI (Electromagnetic Power Supply Voltage: +7 V to +18 V Emission) noise of AM frequency band in comparison Absolute Maximum Rating of BAT: -0.3 V to +40 V with BD41000AFJ-C. BD41001FJ-C is a transceiver for Absolute Maximum Rating of BUS: -27 V to +40 V the CXPI (Clock Extension Peripheral Interface) Power OFF Mode Current: 3 A (Typ) communication. Switching between Master/Slave Mode Operating Temperature Range: -40 C to +125 C can be done using the external pin (the MS pin). Low power consumption during standby (non-communication) using Power Saving function. Arbitration function stops Package W(Typ) x D(Typ) x H(Max) transmitter output upon the detection of BUS data SOP-J8 4.90 mm x 6.00 mm x 1.65 mm collision. Also Fail-safe function stops transmitter output upon the detection of under voltage or temperature abnormality. Features (Note 1) AEC-Q100 Qualified CXPI Standards Qualified Transmission Speed Range from 18.8 kbps to 20 kbps Master/Slave Switching Function Microcontroller Interface Corresponds to 3.3 V/5.0 V Built-in Terminator (30 k(Typ)) Power Saving Function Data Arbitration Function SOP-J8 Built-in Under Voltage Lockout (UVLO) Function Built-in Thermal Shutdown (TSD) Function Low Electro Magnetic Interference (EMI) High Electro Magnetic Susceptibility (EMS) High Electro Static Discharge (ESD) Robustness (Note 1) Grade 1 Applications Automotive Networks Typical Application Circuit CXPI VECU BUS Master node Regulator 10k 2.7k VDD MS(8) INT BAT(7) RXD RXD(1) 100nF Micro TXD TXD(4) Controller BD41001FJ-C (Note 2) 1k CLK CLK(3) BUS(6) NSLP(2) I/O 1nF GND GND(5) Slave node Regulator (Note 3) 10k 2.7k 2.7k VDD INT MS(8) BAT(7) RXD RXD(1) 100nF Micro TXD TXD(4) Controller BD41001FJ-C (Note 2) CLK CLK(3) BUS(6) I/O NSLP(2) 220pF GND GND(5) (Note 2) INT: Interrupt, RXD: UART RXD, TXD: UART TXD, CLK: Clock, I/O: General Purpose I/O (Note 3) While using slave, it is no problem that the CLK pin is opened in the case of non-using the CLK output. Figure 1. Typical Application Circuit Consider the actual application design confirming the following linked document before applying this product. Application Note Product structure : Silicon monolithic integrated circuit This product has no designed protection against radioactive rays w ww.rohm.com TSZ02201-0E2E0H600200-1-2 2018 ROHM Co., Ltd. All rights reserved. 1/21 TSZ22111 14 001 26.Mar.2019 Rev.002 BD41001FJ-C Pin Configuration (TOP VIEW) RXD MS 1 8 NSLP BAT 2 7 CLK 3 6 BUS TXD GND 4 5 Figure 2. Pin Configuration Pin Description Table 1. Pin Description Pin No. Pin Name Function 1 RXD Received data output pin Power saving control input pin 2 NSLP (H: Change to Codec Mode, L: Change to Power OFF Mode) Clock signal input/output pin 3 CLK (Master setting: Input, Slave setting: Output) 4 TXD Transmission data input pin 5 GND Ground 6 BUS CXPI BUS pin 7 BAT Power supply pin Master/Slave switching pin 8 MS (H: Master, L: Slave) Block Diagram 7 BAT BAT Thermal Under Voltage Power on Shutdown Lockout Reset Regulator (TSD) (UVLO) (POR) To each block MS 8 LOGIC Low Pass 1 RXD 6 BUS Filter Decoder Wakeup Timer Slope Control 4 TXD Arbiter Encoder Dominant Timeout Counter (DTC) Controller Slope NSLP 2 Timer 3 CLK Timing Generator Oscillator 5 GND Figure 3. Block Diagram www.rohm.com TSZ02201-0E2E0H600200-1-2 2018 ROHM Co., Ltd. All rights reserved. 2/21 TSZ22111 15 001 26.Mar.2019 Rev.002