ISL98001 Data Sheet September 21, 2010 FN6148.5 Triple Video Digitizer with Digital PLL Features The ISL98001 3-Channel, 8-bit Analog Front-End (AFE) 140MSPS, 170MSPS, 210MSPS, and 275MSPS contains all the functions necessary to digitize analog YPbPr maximum conversion rates video signals and RGB graphics signals from DVD players, Glitchless Macrovision-compliant sync separator digital VCRs, video set-top boxes, and personal computers. Extremely fast recovery from VCR head switching This product familys conversion rates support HDTV resolutions up to 1080p and PC monitor resolutions up to Low PLL clock jitter (250ps 170MSPS) P-P UXGA and QXGA, while the front end s programmable input 64 intrapixel sampling positions bandwidth ensures sharp, clear images at all resolutions. 0.35V to 1.4V video input range P-P P-P To maximize performance with the widest variety of video sources, the ISL98001 features a fast-responding digital PLL Programmable bandwidth (100MHz to 780MHz) (DPLL), providing extremely low jitter with PC graphics signals 2-channel input multiplexer and quick recovery from VCR head switching with video RGB 4:4:4 and YUV 4:2:2 output formats signals. Integrated HSYNC and SOG processing eliminate the need for external slicers, sync separators, Schmitt triggers, 5 embedded voltage regulators allow operation from and filters. single 3.3V supply and enhance performance, isolation Glitchless, automatic Macrovision-compliance is obtained Completely independent 8-bit gain/10-bit offset control by a digital Macrovision detection function that detects and Pb-free (RoHS compliant) automatically removes Macrovision from the HSYNC signal. Applications Ease-of-use is also emphasized with features such as the elimination of PLL charge pump current/VCO range Digital TVs programming and single-bit switching between RGB and Projectors YPbPr signals. Automatic Black Level Compensation (ABLC) eliminates part-to-part offset variation, ensuring perfect black Multifunction monitors level performance in every application. Digital KVM The ISL98001 is fully backwards compatible (hardware and RGB graphics processing software) with the X980xx family of AFEs. Simplified Block Diagram OFFSET VOLTAGE ABLC DAC CLAMP 3 RGB/YPbPr 1 8 OR 16 IN 8-BIT ADC PGA + RGB/YUV OUT 3 RGB/YPbPr 2 IN x3 HSYNC OUT VSYNC OUT SOG 1/2 IN HS OUT SYNC HSYNC 1/2 DIGITAL PLL IN PROCESSING PIXELCLK OUT VSYNC 1/2 IN AFE CONFIGURATION AND CONTROL CAUTION: These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.ISL98001 Ordering Information MAXIMUM TEMPERATURE PART NUMBER PIXEL RATE RANGE PACKAGE PKG. (Note) (MHz) (C) (Pb-free) DWG. ISL98001IQZ-140 140 -40 to +85 128 MQFP MDP0055 ISL98001CQZ-140 140 0 to +70 128 MQFP MDP0055 ISL98001CQZ-170 170 0 to +70 128 MQFP MDP0055 ISL98001CQZ-210 210 0 to +70 128 MQFP MDP0055 ISL98001CQZ-275 275 0 to +70 128 MQFP MDP0055 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Block Diagram V CLAMP 10 OFFSET ABLC DAC R 1 IN V + IN 8 R 7:0 P 8 8-BIT ADC PGA + V - IN 8 R 2 R 7:0 IN S V CLAMP 10 OFFSET ABLC DAC G 1 IN V + IN 8 RGB 1 GND G 7:0 P 8 8-BIT ADC PGA + 8 V - IN G 7:0 G 2 S IN RGB 2 GND V CLAMP OFFSET 10 ABLC DAC B 1 IN V + IN 8 B 7:0 P 8 8-BIT ADC PGA + 8 V - IN B 7:0 S B 2 IN DATACLK SOG 1 IN DATACLK SOG 2 IN HSYNC 1 IN SYNC AFE CONFIGURATION HS OUT PROCESSING AND CONTROL HSYNC 2 IN VSYNCIN1 VS OUT VSYNC 2 IN HSYNC OUT VSYNC OUT CLOCKINV DIGITAL PLL XTAL IN XCLK OUT XTAL OUT SCL SERIAL SDA INTERFACE SADDR FN6148.5 2 September 21, 2010 OUTPUT DATA FORMATTER