DATASHEET 64-pin CK505 Compatible Clock w/Fully Integrated Voltage 9LRS3165B Regulator + Integrated Series Resistor Recommended Application: Pin Configuration CK505 compatible clock with fully integrated voltage regulator and PCI0/CR A 1 64 SCLK Internal series resistor on differential outputs VDDPCI 2 63 SDATA PCI1/CR B 3 62 REF/FSLC/TEST SEL PCI2/TME 4 61 VDDREF Output Features: PCI3 5 60 X1 2 - CPU differential low power push-pull pairs PCI4/27 SEL 6 59 X2 9 - SRC differential low power push-pull pairs PCI5 F/ITP EN 7 58 GNDREF GNDPCI 8 57 FSLB/TEST MODE 1 - CPU/SRC selectable differential low power push-pull pair VDD48 9 56 CK PWRGD/PD 1 - SRC/DOT selectable differential low power push-pull pair USB48M/FSLA 10 55 VDDCPU GND48 11 54 CPUT LR0 5 - PCI, 33MHz VDDI/O96MHz 12 53 CPUC LR0 1 - PCI F, 33MHz free running DOT96T/SRCT LR0 13 52 GNDCPU DOT96C/SRCC LR0 14 51 CPUT F LR1 1 - USB, 48MHz GND 15 50 CPUC F LR1 1 - REF, 14.318MHz VDD 16 49 VDDCPU IO 27FIX/LCDT/SRCT LR1/SE1 17 48 NC 27SS/LCDC/SRCC LR1/SE2 18 47 CPUT ITP LR2/SRCT8 Key Specifications: GND 19 46 CPUC ITP LR2/SRCC8 CPU outputs cycle-cycle jitter < 85ps VDDPLL3I/O 20 45 VDDSRCI/O SRCT LR2/SATACLKT 21 44 SRCT LR7/CR F SRC output cycle-cycle jitter < 125ps SRCC LR2/SATACLKC 22 43 SRCC LR7/CR E PCI outputs cycle-cycle jitter < 250ps GNDSRC 23 42 GNDSRC SRCT LR3/CR C 24 41 SRCT LR6 +/- 100ppm frequency accuracy on CPU & SRC clocks SRCC LR3/CR D 25 40 SRCC LR6 VDDSRCI/O 26 39 VDDSRC SRCT LR4 27 38 PCI STOP Features/Benefits: SRCC LR4 28 37 CPU STOP Does not require external pass transistor for voltage regulator GNDSRC 29 36 VDDSRCI/O SRCT LR9 30 35 SRCC LR10 Integrated 33ohm series resistors on differential outputs, SRCC LR9 31 34 SRCT LR10 Z =50 o SRCC LR11/CR G 32 33 SRCT LR11/CR H Supports spread spectrum modulation, default is 0.5% down 64-TSSOP spread Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Selectable between one SRC differential push-pull pair and two single-ended outputs Meets PCIEX Gen2 specification on dedicated SRC outputs. Muxed SRC outputs meet PCIEX Gen1 specification, except SRC1. Single-ended programmable slew rate control for RFI reduction Table 1: CPU Frequency Select Table 2 1 1 FS C FS B FS A CPU SRC PCI REF USB DOT L L L Meets PCIEX <85ps cycle-to-cycle jitter for SRC 11:1 MHz MHz MHz MHz MHz MHz B0b7 B0b6 B0b5 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 0 1 1 166.66 100.00 33.33 14.318 48.00 96.00 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 11 1 Reserved 1. FS A and FS B are low-threshold inputs.Please see V and V specifications in L L IL FS IH FS the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS C is a three-level input. Please see the V and V L IL FS IH FS specifications in the Input/Supply/Common Output Parameters Table for correct values. IDT 64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1533B01/06/15 1 ICS9LRS3165B9LRS3165B 64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor TSSOP Pin Description Pin Pin Name Type DESCRIPTION 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR A EN bit located in byte 5 of SMBUs address space. 1 PCI0/CR A I/O Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR A enabled. Byte 5, bit 6 controls whether CR A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR A controls SRC0 pair (default), 1= CR A controls SRC2 pair 2 VDDPCI PWR Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR B EN bit located in byte 5 of SMBUs address space. 3 PCI1/CR B I/O Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR B enabled. Byte 5, bit 4 controls whether CR B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR B controls SRC1 pair (default) 1= CR B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows 4 PCI2/TME I/O 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 5 PCI3 OUT 3.3V PCI clock output. 3.3V PCI clock output / 27MH mode select for pin17, 18 strap. On powerup, the 6 PCI4/27 SEL I/O logic value on this pin determines the power-up default of DOT 96/SRC0 and 27MHz/SRC1 output and the function table for the pin17 and pin18. Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI STOP pin. On powerup, the state of this pin 7 PCI5 F/ITP EN I/O determines whether pins 46 and 47 are an ITP or SRC pair. 0 =SRC8/SRC8 1 = ITP/ITP 8 GNDPCI PWR Ground for PCI clocks. 9 VDD48 PWR Power supply for USB clock, nominal 3.3V. Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency 10 USB48M/FSLA I/O selection. Refer to input electrical characteristics for Vil FS and Vih FS values. 11 GND48 PWR Ground pin for the 48MHz outputs. 12 VDDI/O96MHz PWR 1.05V to 3.3V from external power supply True clock of SRC or DOT96. The power-up default function depends on 13 DOT96T/SRCT LR0 OUT 27 Select,1= SRC0, 0=DOT96 Complement clock of SRC or DOT96. The power-up default function depends 14 DOT96C/SRCC LR0 OUT on 27 Select,1= SRC0, 0=DOT96 15 GND PWR Ground pin for the DOT96 clocks. 16 VDD PWR Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal. IDT 64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1533B01/06/15 2