Integrated ICS951462 Circuit Systems, Inc. TM Programmable System Clock Chip for ATI RS/RD690 - K8 based Systems Recommended Application: Pin Configuration ATI RS/RD690 systems using AMD K8 processors & SB600 GNDREF 1 64 FS0/REF0 Southbridge VDDREF 2 63 FS1/REF1 X1 3 62 FS2/REF2 Output Features: X2 4 61 PD** 2 - pairs of CPU pairs VDD48 5 60 VDDHTT 8 - pairs of SRC pairs 48MHz 0 6 59 HTTCLK0 4 - pairs of ATIG pairs 48MHz 1 7 58 GNDHTT GND48 8 57 *CLKREQA 1 - HyperTransport 66MHz clock seed SMBCLK 9 56 CPUCLK8T0 2 - 48MHz USB clock SMBDAT 10 55 CPUCLK8C0 3 - 14.318MHz Reference clock RESET IN 11 54VDDCPU SRCCLKT7 12 53 GNDCPU Key Specifications: SRCCLKC7 13 52 CPUCLK8T1 CPU outputs cycle-to-cycle jitter < 85ps VDDSRC 14 51 CPUCLK8C1 GNDSRC 15 50 VDDA SRC outputs cycle-to-cycle jitter < 125ps SRCCLKT6 16 49 GNDA ATIG outputs cycle-to-cycle jitter < 125ps SRCCLKC6 17 48 IREF +/- 300ppm frequency accuracy on CPU, SRC & ATIG SRCCLKT5 18 47 SRCCLKT0 clocks SRCCLKC5 19 46 SRCCLKC0 SRCCLKT4 20 45 GNDSRC Features/Benefits: SRCCLKC4 21 44 VDDSRC GNDSRC 22 43 SRCCLKT1 3 - Programmable Clock Request pins for SRC and ATIG clocks VDDSRC 23 42 SRCCLKC1 SRCCLKT3 24 41 ATIGCLKT0 ATIGCLKs are programmable for frequency SRCCLKC3 25 40 ATIGCLKC0 Spread Spectrum for EMI reduction SRCCLKT2 26 39 VDDATIG Outputs may be disabled via SMBus SRCCLKC2 27 38 GNDATIG External crystal load capacitors for maximum frequency VDDSRC 28 37 ATIGCLKT1 accuracy GNDSRC 29 36 ATIGCLKC1 ATIGCLKT330 35ATIGCLKT2 Functionality ATIGCLKC3 31 34 ATIGCLKC2 SRC ATIG USB CPU HTT *CLKREQB 32 33*CLKREQC FS2 FS1 FS0 MHz MHz MHz MHz MHz 64-TSSOP 000Hi-Z Hi-Z 100.00 100.00 48.00 * Internal Pull-Up Resistor 001 X / 2 X / 3 100.00 100.00 48.00 ** Internal Pull-Down Resistor 0 1 0 230.00 76.67 100.00 100.00 48.00 100.00 100.00 48.00 0 1 1 240.00 80.00 100.00 100.00 48.00 1 0 0 100.00 66.66 1 0 1 133.33 66.66 100.00 100.00 48.00 1 1 0 166.67 66.66 100.00 100.00 48.00 100.00 100.00 48.00 1 1 1 200.00 66.66 Power Groups Pin Number Description VDD GND 5 8 USB 48 outputs 14,23,28,44 15,22,29,45 SRCCLK outputs 39 38 ATIGCLK differential outputs 50 49 Analog, PLL 54 53 CPUCLK8 differential outputs 60 58 HTTCLK output 2 1 REF outputs 1094J03/16/09 *Other names and brands may be claimed as the property of others. ICS 951462Integrated ICS951462 Circuit Systems, Inc. Pin Description PIN PIN NAME TYPE DESCRIPTION 1 GNDREF PWR Ground pin for the REF outputs. 2 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 3 X1 IN Crystal input, Nominally 14.318MHz. 4 X2 OUT Crystal output, Nominally 14.318MHz 5 VDD48 PWR Power pin for the 48MHz output.3.3V 6 48MHz 0 OUT 48MHz clock output. 7 48MHz 1 OUT 48MHz clock output. 8 GND48 PWR Ground pin for the 48MHz outputs 9 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant 10 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant Real time active low input. When active, SMBus is reset to power up 11 RESET IN IN default. 12 SRCCLKT7 OUT True clock of differential SRC clock pair. 13 SRCCLKC7 OUT Complement clock of differential SRC clock pair. 14 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 15 GNDSRC PWR Ground pin for the SRC outputs 16 SRCCLKT6 OUT True clock of differential SRC clock pair. 17 SRCCLKC6 OUT Complement clock of differential SRC clock pair. 18 SRCCLKT5 OUT True clock of differential SRC clock pair. 19 SRCCLKC5 OUT Complement clock of differential SRC clock pair. 20 SRCCLKT4 OUT True clock of differential SRC clock pair. 21 SRCCLKC4 OUT Complement clock of differential SRC clock pair. 22 GNDSRC PWR Ground pin for the SRC outputs 23 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 24 SRCCLKT3 OUT True clock of differential SRC clock pair. 25 SRCCLKC3 OUT Complement clock of differential SRC clock pair. 26 SRCCLKT2 OUT True clock of differential SRC clock pair. 27 SRCCLKC2 OUT Complement clock of differential SRC clock pair. 28 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 29 GNDSRC PWR Ground pin for the SRC outputs 30 ATIGCLKT3 OUT True clock of differential ATIGCLK clock pair. 31 ATIGCLKC3 OUT Complementary clock of differential ATIGCLK clock pair. Output enable for PCI Express (SRC) outputs. SMBus selects which 32 *CLKREQB IN outputs are controlled. 0 = enabled, 1 = tri-stated 1094J03/16/09 2