89HPES48T12G2 48-Lane 12-Port PCIe Gen2 Data Sheet System Interconnect Switch De-emphasis Device Overview Receive equalization The 89HPES48T12G2 is a member of the IDT PRECISE family of PCI Express switching solutions. The PES48T12G2 is a 48-lane, 12- Drive strength port system interconnect switch optimized for PCI Express Gen2 packet Initialization / Configuration switching in high-performance applications, supporting multiple simulta- Supports Root (BIOS, OS, or driver), Serial EEPROM, or neous peer-to-peer traffic flows. Target applications include servers, SMBus switch initialization storage, communications, embedded systems, and multi-host or intelli- Common switch configurations are supported with pin strap- gent I/O based systems with inter-domain communication. ping (no external components) Supports in-system Serial EEPROM initialization/program- Features ming High Performance Non-Blocking Switch Architecture Quality of Service (QoS) 48-lane 12-port PCIe switch Port arbitration Six x8 ports switch ports each of which can bifurcate to two Round robin x4 ports (total of twelve x4 ports) Weighted Round Robin (WRR) Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s Gen1 operation Request metering Delivers up to 48 GBps (384 Gbps) of switching capacity IDT proprietary feature that balances bandwidth among switch ports for maximum system throughput Supports 128 Bytes to 2 KB maximum payload size High performance switch core architecture Low latency cut-through architecture Combined Input Output Queued (CIOQ) switch architecture Supports one virtual channel and eight traffic classes with large buffers Standards and Compatibility Multicast PCI Express Base Specification 2.0 compliant Compliant to the PCI-SIG multicast ECN Implements the following optional PCI Express features Supports arbitrary multicasting of Posted transactions Advanced Error Reporting (AER) on all ports Supports 64 multicast groups Multicast overlay mechanism support End-to-End CRC (ECRC) ECRC regeneration support Access Control Services (ACS) Clocking Power Budgeting Enhanced Capability Supports 100 MHz and 125 MHz reference clock frequencies Device Serial Number Enhanced Capability Flexible clocking modes Sub-System ID and Sub-System Vendor ID Capability Common clock Internal Error Reporting ECN Non-common clock Multicast ECN Hot-Plug and Hot Swap VGA and ISA enable Hot-plug controller on all ports L0s and L1 ASPM Hot-plug supported on all downstream switch ports ARI ECN 2 Port Configurability All ports support hot-plug using low-cost external I C I/O expanders x4 and x8 ports Configurable presence detect supports card and cable appli- Ability to merge adjacent x4 ports to create a x8 port cations Automatic per port link width negotiation GPE output pin for hot-plug event notification (x8 x4 x2 x1) Enables SCI/SMI generation for legacy operating system Crosslink support support Automatic lane reversal Hot swap capable I/O Autonomous and software managed link width and speed Power Management control Supports D0, D3hot and D3 power management states Per lane SerDes configuration IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 43 November 28, 2011IDT 89HPES48T12G2 Data Sheet Active State Power Management (ASPM) The PES48T12G2 is based on a flexible and efficient layered archi- tecture. The PCI Express layer consists of SerDes, Physical, Data Link Supports L0, L0s, L1, L2/L3 Ready and L3 link states and Transaction layers in compliance with PCI Express Base specifica- Configurable L0s and L1 entry timers allow performance/ tion Revision 2.0. The PES48T12G2 can operate either as a store and power-savings tuning forward or cut-through switch. It supports eight Traffic Classes (TCs) Supports PCI Express Power Budgeting Capability and one Virtual Channel (VC) with sophisticated resource management SerDes power savings to enable efficient switching and I/O connectivity for servers, storage, Supports low swing / half-swing SerDes operation and embedded processors with limited connectivity. SerDes optionally turned-off in D3hot SerDes associated with unused ports are turned-off SerDes associated with unused lanes are placed in a low power state 9 General Purpose I/O Reliability, Availability and Serviceability (RAS) ECRC support AER on all ports SECDED ECC protection on all internal RAMs End-to-end data path parity protection Checksum Serial EEPROM content protected Autonomous link reliability (preserves system operation in the presence of faulty links) Ability to generate an interrupt (INTx or MSI) on link up/down transitions Test and Debug On-chip link activity and status outputs available for Port 0 (upstream port) Per port link activity and status outputs available using 2 external I C I/O expander for all other ports SerDes test modes Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG Power Supplies Requires only two power supply voltages (1.0 V and 2.5 V) Note that a 3.3V is preferred for V I/O DD No power sequencing requirements Packaged in a 27mm x 27mm 676-ball Flip Chip BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES48T12G2 provides the most efficient fan-out solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 48 GBps (384 Gbps) of aggregated, full-duplex switching capacity through 48 integrated serial lanes, using proven and robust IDT technology. Each lane provides 5 Gbps of band- width in both directions and is fully compliant with PCI Express Base Specification, Revision 2.0. 2 of 43 November 28, 2011