Product Information

PE43705B-Z

PE43705B-Z electronic component of pSemi

Datasheet
Attenuators 50? 7Bit 31.75dB 0.25dB 0.5dB 1.0dB Digital Step Attenuator wo ext. Vss

Manufacturer: pSemi
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Price (AUD)

1: AUD 29.6731 ( AUD 32.64 Inc GST) ea
Line Total: AUD 29.6731 ( AUD 32.64 Inc GST)

5720 - Global Stock
Ships to you between
Thu. 18 Jul to Mon. 22 Jul
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
2316 - Global Stock


Ships to you between Thu. 18 Jul to Mon. 22 Jul

MOQ : 1
Multiples : 1
1 : AUD 23.0708
100 : AUD 16.4892
1000 : AUD 11.6238
3000 : AUD 10.3146
6000 : AUD 10.1554

     
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Product Specification PE43705 UltraCMOS RF Digital Step Attenuator, 7-bit, 31.75 dB 50 MHz 8 GHz Product Description Features The PE43705 is a 50 , HaRP technology-enhanced, 7-bit RF digital step attenuator (DSA) designed for use in 3G/4G Attenuation options: covers a 31.75 dB wireless infrastructure and other high performance RF range in 0.25 dB, 0.5 dB, or 1.0 dB steps applications. 0.25 dB monotonicity for 6 GHz 0.50 dB monotonicity for 7 GHz This DSA is a pin-compatible upgraded version of PE43703 with higher power handling and a wider frequency, control 1.00 dB monotonicity for 8 GHz voltage and operating temperature range. An integrated Safe attenuation state transitions digital control interface supports both serial and parallel High power handling programming of the attenuation, including the capability to 31 dBm, Pulsed 8 GHz program an initial attenuation state at power-up. 28 dBm, CW 8 GHz Covering a 31.75 dB attenuation range in 0.25 dB, 0.50 dB, High linearity: +58 dBm IIP3 or 1 dB steps, it maintains a monotonic step response from 1.8V control logic compatible 50 MHz through 8 GHz. PE43705 also features safe 105C operating temperature attenuation state transitions and is offered in a 32-lead Programming modes 5x5 mm QFN package. In addition, no external blocking capacitors are required if 0V DC is present on the RF ports. Direct Parallel Latched Parallel The PE43705 is manufactured on pSemis UltraCMOS Serial process, a patented variation of silicon-on-insulator (SOI) Serial Addressable technology on a sapphire substrate. High-attenuation state power-up (PUP) pSemis HaRP technology enhancements deliver high ESD performance linearity and excellent harmonics performance. It is an 1.5 kV HBM on all pins innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 2. Package Type Figure 1. Functional Diagram 32-lead 5x5 mm QFN 71-0052 Document No. DOC-89603-2 www.psemi.com 20182020 pSemi Corporation All rights reserved. Page 1 of 18 PE43705 Product Specification Table 1. Electrical Specifications: 0.25 dB steps +25C, V = 2.3V to 5.5V, (Z = Z = 50 ), DD S L unless otherwise noted Parameter Condition Frequency Min Typ Max Unit Operating frequency 50 6000 MHz Attenuation range 0.25 dB step 0 31.75 dB 50 MHz 2.2 GHz 1.3 1.6 dB Insertion loss 2.2 GHz 4 GHz 1.7 2.0 dB 4 GHz 6 GHz 2.4 2.8 dB + (0.15 + 1.5% of dB attenuation setting) 50 MHz 2.2 GHz (0.1 + 1% of dB attenuation setting) + (0.15 + 3% of dB attenuation setting) 0 dB 15.75 dB Attenuation settings >2.2 GHz 4 GHz (0.1 + 1% of dB attenuation setting) + (0.2 + 6% of dB attenuation setting) >4 GHz 6 GHz (0.15 + 1% of dB attenuation setting) Attenuation error + (0.15 + 1.5% dB attenuation Setting) 50 MHz 2.2 GHz (0.1 + 1.5% of dB attenuation setting) + (0.15 + 4% dB attenuation Setting) 16 dB 31.75 dB Attenuation settings >2.2 GHz 4 GHz (0.1 + 0.75% of dB attenuation setting) + (0.25 + 7.5% of dB attenuation setting) >4 GHz 6 GHz (0.2 + 0% of dB attenuation setting) 50 MHz 4 GHz 20 dB Return loss Input port 4 GHz 6 GHz 15 dB 50 MHz 4 GHz 17 dB Return loss Output port 4 GHz 6 GHz 13 dB Relative phase 0 dB 31.75 dB Attenuation settings 50 MHz 6 GHz 55 deg 1 Input 0.1dB compression point 50 MHz 6 GHz 34 dBm Input IP3 Two tones at +20 dBm, 500 kHz spacing 50 MHz 6 GHz 58 dBm RF Trise/Tfall 10% / 90% RF 568 ns Switching time 50% CTRL to 90% or 10% RF 1 s Note 1: The input 0.1dB compression point is a linearity figure of merit. Refer to Table 5 for the operating RF input power (50). 20182020 pSemi Corporation All rights reserved. Document No. DOC-89603-2 Page 2 of 18

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:
Peregrine
PEREGRINE SEMICONDUCTOR

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