PE43650 Document Category: Product Specification 50 RF Digital Attenuator 5-bit, 15.5 dB, 9 kHz - 6 GHz Features Figure 1 PE43650 Functional Diagram Attenuation: 0.5 dB steps to 15.5 dB Switched Attenuator Array High linearity: Typical +58 dBm IP3 RF RF Input Output Excellent low-frequency performance Programming modes: Direct parallel Latched parallel Serial CMOS-compatible Parallel No DC blocking capacitors required Control Packaged in a 24-lead 4x4x0.85 mm QFN 5 Serial In Control Logic Interface Applications CLK 3G / 4G wireless infrastructure RF/IF gain control LE Base stations (BTS) and remote radio heads (RRH) Optical and RF repeaters P/S Distributed antenna system (DAS) Land mobile radio system Point-to-point communication system Product Description The PE43650 is a high linearity, 5-bit RF Digital Step Attenuator (DSA). This highly versatile DSA covers a 15.5 dB attenuation range in 0.5 dB steps. The Peregrine 50 RF DSA provides multiple CMOS control interfaces. It maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. Performance does not change with VDD due to on-board regulator. This Peregrine DSA is available in a 4x4 mm 24-lead QFN footprint. The PE43650 is manufactured on Peregrines UltraCMOS process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. 2018, pSemi Corporation. All rights reserved. Headquarters: 9369 Carroll Park Drive, San Diego, CA, 92121 Product Specification DOC-88239-3 (06/2019) www.psemi.comPE43650 50 RF Digital Attenuator Absolute Maximum Ratings Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. ESD Precautions When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 1. Latch-up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 1 Absolute Maximum Ratings for PE43650 Parameter/Condition Min Max Unit Power supply voltage (V ) -0.3 6.0 V DD Voltage on any Digital input (V ) -0.3 5.8 V I Storage temperature range (T ) -65 150 C ST Input power (50) (P ) IN 9 kHz 20 MHz Fig. 2 dBm 20 MHz 6 GHz +23 dBm (*) 500 V ESD voltage (HBM) 100 V ESD voltage (machine model) Note: * Human Body Model (HBM, MIL STD 883 Method 3015.7) Figure 2 Maximum Power Handling Capability Page 2 of 17 DOC-88239-3 (06/2019) www.psemi.com