Product Information

NCV7420D26R2G

NCV7420D26R2G electronic component of ON Semiconductor

Datasheet
LIN Transceivers EMC IMPR. LIN + 5V REGULATOR

Manufacturer: ON Semiconductor
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (AUD)

1: AUD 3.0119 ( AUD 3.31 Inc GST) ea
Line Total: AUD 3.0119 ( AUD 3.31 Inc GST)

2902 - Global Stock
Ships to you between
Fri. 26 Jul to Tue. 30 Jul
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
2901 - Global Stock


Ships to you between Fri. 26 Jul to Tue. 30 Jul

MOQ : 1
Multiples : 1

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NCV7420D26R2G
ON Semiconductor

1 : AUD 2.9015
10 : AUD 2.4946
100 : AUD 2.0523
250 : AUD 1.8577
500 : AUD 1.7869
1000 : AUD 1.5021
3000 : AUD 1.5021
6000 : AUD 1.4578
9000 : AUD 1.4348

     
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NCV7420 NCV7420 LIN Transceiver with 3.3 V or 5 V Voltage Regulator General Description The NCV7420 is a fully featured local interconnect network (LIN) www.onsemi.com transceiver designed to interface between a LIN protocol controller and the physical bus. The transceiver is implemented in I3T PIN CONFIGURATION technology enabling both highvoltage analog circuitry and digital 1 14 functionality to coexist on the same chip. V V BB CC 2 13 14 The NCV7420 LIN device is a member of the invehicle LIN RxD 3 12 1 networking (IVN) transceiver family of ONSemiconductor that GND TxD 4 11 integrates a LIN v2.0/2.1 physical transceiver and either a 3.3 V or a SOIC14 GND GND 5 10 5 V voltage regulator. D SUFFIX WAKE STB The LIN bus is designed to communicate low rate data from control CASE 751AP 6 9 INH EN devices such as door locks, mirrors, car seats, and sunroofs at the 7 8 OTP ZAP TEST lowest possible cost. The bus is designed to eliminate as much wiring as possible and is implemented using a single wire in each node. Each node has a slave MCUstate machine that recognizes and translates the instructions specific to that function. The main attraction of the ORDERING INFORMATION LIN bus is that all the functions are not time critical and usually relate See detailed ordering and shipping information in the package dimensions section on page 19 of this data sheet. to passenger comfort. KEY FEATURES LINBus Transceiver EMI Compatibility LIN compliant to specification revision 2.0 and 2.1 Integrated slope control (backward compatible to version 1.3) and J2602 Meets most demanding EMS/EME requirements I3T high voltage technology Modes Bus voltage 45 V Normal mode: LIN communication in either low (up to Transmission rate up to 20 kBaud 10 kBaud) or normal slope Sleep mode: V is switched off and no Protection CC communication on LIN bus Thermal shutdown Standby mode: V is switched on but there is no CC Indefinite shortcircuit protection on pins LIN and communication on LIN bus WAKE towards supply and ground Wakeup bringing the component from sleep mode into Load dump protection (45 V) standby mode is possible either by LIN command or Bus pins protected against transients in an automotive digital input signal on WAKE pin. Wakeup from LIN environment bus can also be detected and flagged when the chip is System ESD protection level for LIN, WAKE and V BB already in standby mode. up to 12 kV Quality Voltage Regulator NCV Prefix for Automotive and Other Applications Output voltage 5 V / ~50 mA or 3.3 V / ~50 mA Requiring Unique Site and Control Change Require Wakeup input ments AECQ100 Qualified and PPAP Capable Enable inputs for standby and sleep mode These Devices are PbFree, Halogen Free/BFR Free INH output for auxiliary purposes (switching of an and are RoHS Compliant external pullup or resistive divider towards battery, control of an external voltage regulator etc.) Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: May, 2015 Rev. 9 NCV7420/DNCV7420 MARKING DIAGRAM 14 NCV7420 = Specific Device Code x = 3 = NCV7420D23G NCV7420x = 4 = NCV7420D24G AWLYWWG = 5 = NCV7420D25G = 6 = NCV7420D26G 1 A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week G = PbFree Package Table 1. KEY TECHNICAL CHARACTERISTICS 3.3 V version Symbol Parameter Min Typ Max Unit V Nominal battery operating voltage (Note 1) 5 12 26 V BB Load dump protection (Note 2) 45 I Supply current in sleep mode 20 A BB SLP V Regulated V output, V load 1 mA30 mA 3.23 3.30 3.37 V CC OUT CC CC (Note 4) Regulated V output, V load 0 mA50 mA 3.19 3.30 3.41 CC CC I Maximum V output current (Note 3) 50 mA OUT MAX CC V Operating DC voltage on WAKE pin 0 V V WAKE BB Maximum rating voltage on WAKE pin 45 45 T Junction thermal shutdown temperature 165 195 C JSD T Operating junction temperature 40 +150 C J Table 2. KEY TECHNICAL CHARACTERISTICS 5 V version Symbol Parameter Min Typ Max Unit V Nominal battery operating voltage (Note 1) 6 12 26 V BB Load dump protection 45 I Supply current in sleep mode 20 A BB SLP V Regulated V output, V load 1 mA30 mA 4.9 5.0 5.1 V CC OUT CC CC (Note 4) Regulated V output, V load 0 mA50 mA 4.83 5.0 5.17 CC CC I Maximum V output current (Note 3) 50 mA OUT MAX CC V Operating DC voltage on WAKE pin 0 V V WAKE BB Maximum rating voltage on WAKE pin 45 45 T Junction thermal shutdown temperature 165 195 C JSD T Operating junction temperature 40 +150 C J 1. Below 5 V on V in normal mode, the bus will either stay recessive or comply with the voltage level specifications and transition time BB specifications as required by SAE J2602. It is ensured by the battery monitoring circuit. 2. The applied transients shall be in accordance with ISO 7637 part 1, test pulse 5. The device complies with functional class C class A can be reached depending on the application and external conditions. 3. Thermal aspects of the entire endapplication have to be taken into account in order to avoid thermal shutdown of NCV7420. 4. V voltage regulator output must be properly decoupled by external capacitor of min. 8 F with ESR < 1 to ensure stability. CC Table 3. THERMAL CHARACTERISTICS Symbol Parameter Conditions Value Unit R Thermal resistance junctiontoambient, 1S0P PCB (Note 5) free air 140 K/W JA1 R 2 Thermal resistance junctiontoambient, 2S2P PCB (Note 6) free air 80 K/W JA 5. Test board according to EIA/JEDEC Standard JESD513, signal layer with 20% trace coverage 6. Test board according to EIA/JEDEC Standard JESD517, signal layers with 20% trace coverage www.onsemi.com 2

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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ON SEMI
ON Semicon
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