NB3H63143G 3.3 V / 2.5 V Programmable OmniClock Generator with Single Ended (LVCMOS/LVTTL) and Differential (LVPECL/LVDS/ HCSL/CML) Outputs with Individual Output Enable www.onsemi.com and Individual VDDO The NB3H63143G, which is a member of the OmniClock family, is a onetime programmable (OTP), low power PLLbased clock 1 generator that supports any output frequency from 8 kHz to 200 MHz. The device accepts fundamental mode parallel resonant crystal or a QFN16 CASE 485AE single ended (LVCMOS/LVTTL) reference clock as input. It generates either three single ended (LVCMOS/LVTTL) outputs, or MARKING DIAGRAM one single ended output and one differential (LVPECL/LVDS/HCSL/CML) output. The output signals can be 3H631 modulated using the spread spectrum feature of the PLL 43Gxx (programmable spread spectrum type, deviation and rate) for ALYW applications demanding low electromagnetic interference (EMI). Individual output enable pins OE 2:0 are available to enable/disable the outputs. Individual output voltage pins VDDO 2:0 are available 3H63143G = Specific Device Code to independently set the output voltage of each output. Up to four xx = Specific Program Code (Default 00 for Unprogrammed Part) different configurations can be written into the device memory. Two A = Assembly Location selection pins (SEL 1:0 ) allow the user to select the configuration to L = Wafer Lot use. Using the PLL bypass mode, it is possible to get a copy of the Y = Year input clock on any or all of the outputs. The device can be powered W = Work Week down using the Power Down pin (PD ). It is possible to program the = PbFree Package internal input crystal load capacitance and the output drive current (Note: Microdot may be in either location) provided by the device. The device also has automatic gain control (crystal power limiting) circuitry which avoids the device overdriving ORDERING INFORMATION See detailed ordering and shipping information on page 23 of the external crystal. this data sheet. Features Member of the OmniClock Family of Programmable Programmable Internal Crystal Load Capacitors Clock Generators Programmable Output Drive Current for Single Ended Operating Power Supply: 3.3 V 10%, 2.5 V 10% Outputs I/O Standards Power Saving Mode through Power Down Pin Inputs: LVCMOS/LVTTL, Fundamental Mode Programmable PLL Bypass Mode Crystal Programmable Output Inversion Outputs: 1.8 V to 3.3 V LVCMOS/LVTTL Programming and Evaluation Kit Available for Field Outputs: LVPECL, LVDS, HCSL and CML Programming and Quick Evaluation 3 Programmable Single Ended (LVCMOS/LVTTL) Temperature Range 40C to 85C Outputs from 8 kHz to 200 MHz Packaged in 16pin QFN 1 Programmable Differential Clock Output up to These are PbFree Devices 200 MHz Input Frequency Range Typical Applications Crystal: 3 MHz to 50 MHz eBooks and Media Players Reference Clock: 3 MHz to 200 MHz Smart Wearables, Smart Phones, Portable Medical and Configurable Spread Spectrum Frequency Modulation Industrial Equipment Parameters (Type, Deviation, Rate) Set Top Boxes, Printers, Digital Cameras and Individual Output Enable Pins Camcorders Independent Output Voltage Pins Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: January, 2016 Rev. 4 NB3H63143G/DNB3H63143G BLOCK DIAGRAM VDD PD SEL0 SEL1 Input Decoder Output control Configuration Crystal/Clock Control Memory VDDO0 Frequency CMOS/ Output and SS DIFF CLK0 Divider buffer PLL Block XIN/ CLKIN Reference OE0 Clock Buffer/ Clock Crystal Phase Charge VDDO1 VCO Oscillator And Detector Pump Crystal CMOS/ AGC XOUT Output CLK1 DIFF Divider buffer Feedback OE1 Divider VDDO2 Output CMOS CLK2 Divider buffer PLL Bypass Mode OE2 GND GNDO Notes: 1. CLK0 and CLK1 can be configured to be one LVPECL, LVDS, HCSL or CML output, or two single ended LVCMOS/LVTTL outputs. 2. Dotted lines are the programmable control signals to internal IC blocks. 3. OE 2:0 , SEL 1:0 have internal pull up resistors. PD has internal pull down resistor. Figure 1. Simplified Block Diagram PIN FUNCTION DESCRIPTION 16 15 14 13 NB3H63143G XIN/CLKIN 1 12 VDD XOUT 2 11 VDDO1 GNDO (EPAD) PD 3 10 CLK1 GND 4 9 CLK0 5 6 7 8 Figure 2. Pin Connections (Top View) QFN16 (with EPAD) www.onsemi.com 2 OE0 SEL0 OE1 SEL1 OE2 VDDO2 VDDO0 CLK2