TJA1102A 100BASE-T1 dual/single PHY for automotive Ethernet Rev. 1 7 June 2021 Product data sheet 1 General description The TJA1102A is a 100BASE-T1-compliant dual-port Ethernet PHY optimized for automotive use cases such as gateways, IP camera links, radar modules, driver assistance systems and back-bone networks. The device provides 100 Mbit/s transmit and receive capability over two unshielded twisted-pair cables, supporting a cable length of up to at least 15 m. The TJA1102A has been designed for automotive robustness, while minimizing power consumption and system costs. For added flexibility, a single PHY version is available (TJA1102AS) in which one of the PHYs is disabled. Unless otherwise specified, all references in this document to TJA1102A encompass both the dual- and single-PHY variants. The TJA1102A supports OPEN Alliance TC-10-compliant sleep and wake-up request forwarding, with an always-on power domain connected directly to the battery supply without the need for a dedicated voltage regulator. 2 Features and benefits 2.1 General Dual-port 100BASE-T1 PHY single-port operation possible Single-port variant available MII- and RMII-compliant interfaces HVQFN 56-pin package (8 8 mm) 2.2 Optimized for automotive use cases Transmitter optimized for capacitive coupling to unshielded twisted-pair cable Adaptive receive equalizer optimized for automotive cable length of up to at least 15 m Enhanced integrated PAM-3 pulse shaping for low RF emissions EMC-optimized output driver strength for MII and RMII MDI pins meet class IV conducted emission limit as per OPEN Alliance EMC Specification 2.0 MDI pins protected against ESD to 6 kV HBM and 6 kV IEC61000-4-2 MDI pins protected against transients in automotive environment MDI pins do not need external filtering or ESD protection Automotive-grade temperature range from -40 C to +125 C Automotive product qualification in accordance with AEC-Q100 Host-configurable MDI polarity Automated polarity detection and correctionNXP Semiconductors TJA1102A 100BASE-T1 dual/single PHY for automotive Ethernet 2.3 Low-power mode OPEN Alliance TC-10-compliant sleep and wake-up forwarding Robust remote wake-up detection via bus lines Wake-up forwarding at PHY level (supporting global system wake-up) Inhibit output for voltage regulator control Dedicated PHY enable/disable input pin to minimize power consumption Local wake-up pin Wake-up via SMI-access 2.4 Diagnosis Signal Quality Indicator for real-time monitoring of link stability and transmitted data quality Diagnosis of cable errors (shorts and opens) Gap-free supply undervoltage detection with fail-silent behavior Internal, external and remote loopback modes 2.5 Miscellaneous Internal reverse MII mode for repeater operation On-chip regulators to provide 3.3 V single-supply operation Supports optional 1.8 V external supply for digital core On-chip termination resistors for the differential cable pair Jumbo frame support up to 16 kB 3 Ordering information Table 1.Ordering information Type number Package Name Description Version 1 TJA1102AHN HVQFN56 plastic thermal enhanced very thin quad flat package no leads 56 SOT684-13 terminals body 8 8 0.85 mm 2 TJA1102AHN/S 1 Dual PHY. 2 Single PHY. 4 Block diagram A block diagram of the TJA1102A is shown in Figure 1. The 100BASE-T1 sections contain the functional blocks specified in the 100BASE-T1 standard that make up the Physical Coding Sublayer (PCS) and the Physical Medium Attachment (PMA) layer for both the transmit and receive signal paths. The MII/RMII interface (including the Serial Management Interface (SMI)) conforms to IEEE 802.3 clause 22. Additional blocks are defined for mode control, register configuration, interrupt control, system configuration, reset control, local wake-up, remote wake-up, undervoltage detection and configuration control. A number of power-supply-related functional blocks are defined: an internal 1.8 V regulator for the digital core, a Very Low Power (VLP) supply for Sleep mode, the reset circuit, supply monitoring and inhibit control. TJA1102A All information provided in this document is subject to legal disclaimers. NXP B.V. 2021. All rights reserved. Product data sheet Rev. 1 7 June 2021 2 / 67