SC18IM700 2 Master I C-bus controller with UART interface Rev. 4 9 October 2019 Product data sheet 1. General description The SC18IM700 is designed to serve as an interface between the standard UART port of 2 a microcontroller or microprocessor and the serial I C-bus this allows the microcontroller 2 or microprocessor to communicate directly with other I C-bus devices. The SC18IM700 2 2 can operate as an I C-bus master. The SC18IM700 controls all the I C-bus specific sequences, protocol, arbitration and timing. The host communicates with SC18IM700 with ASCII messages protocol this makes the control sequences from the host to the SC18IM700 become very simple. 2. Features and benefits UART host interface 2 I C-bus controller Eight programmable I/O pins High-speed UART: baud rate up to 460.8 kbit/s 2 High-speed I C-bus: 400 kbit/s 16-byte TX FIFO 16-byte RX FIFO Programmable baud rate generator 2.4 V and 3.6 V operation Sleep mode (power-down) 2 UART message format resembles I C-bus transaction format 2 I C-bus master functions Multi-master capability 5 V tolerance on the input pins 8 N 1 UART format (8 data bits, no parity bit, 1 stop bit) Available in very small TSSOP16 package 3. Applications 2 Enable I C-bus master support in a system 2 I C-bus instrumentation and control Industrial control Medical equipment Cellular telephones Handheld computersSC18IM700 NXP Semiconductors 2 Master I C-bus controller with UART interface 4. Ordering information Table 1. Ordering information Type number Topside Package marking Name Description Version SC18IM700IPW/S8 IM700 B TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 4.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method Minimum Temperature order quantity 1 SC18IM700IPW/S8 SC18IM700IPW/S8HP TSSOP16 REEL 13 Q4/T2 2500 T = 40 C to +85 C amb *STANDARD MARK SMD 1 NXP plans to supply the /S8 device with an expected discontinuation in the 2024-2025 timeframe, but in the meantime, Failure Analysis for /S8 devices will consist of Automated Test Equipment (ATE) and electrical overstress verification along with package and wire bond validation only. Detailed device failure analysis will not be available refer to CIN 201708035I. 5. Block diagram V V DD SS SC18IM700 RX TX 2 SDA I C-BUS CONTROLLER SCL UART RESET 8 GPIO GPIOs WAKEUP REGISTER 002aab743 Fig 1. Block diagram of SC18IM700 SC18IM700 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2019. All rights reserved. Product data sheet Rev. 4 9 October 2019 2 of 24