PTN3366 Low power HDMI/DVI level shifter with active DDC buffer, supporting 3 Gbit/s operation Rev. 1.1 22 May 2015 Product data sheet 1. General description PTN3366 is a low power, high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain current-steering differential output signals, up to 3 Gbit/s per lane to support 36-bit deep color mode, 4K 2K video format or 3D video data transport. Each of these lanes provides a level-shifting differential active buffer, with built-in Equalization, to translate from low-swing AC-coupled differential signaling on the source side, to TMDS-type DC-coupled differential current-mode signaling terminated into 50 to 3.3 V on the sink side. Additionally, the PTN3366 provides a single-ended active buffer for voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side and provides a channel with active buffering and level shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The 2 DDC channel is implemented using active I C-bus buffer technology providing redriving and level shifting as well as disablement (isolation between source and sink) of the clock and data lines. The low-swing AC-coupled differential input signals to the PTN3366 typically come from a display source with multi-mode I/O, which supports multiple display standards, for example, DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or HDMI v1.4b specification. By using PTN3366, chip set vendors are able to implement such reconfigurable I/Os on multi-mode display source devices, allowing the support of multiple display standards while keeping the number of chip set I/O pins low. See Figure 1. The PTN3366 main high-speed differential lanes feature low-swing self-biasing differential inputs which are compliant to the electrical specifications of DisplayPort Standard v1.2a and/or PCI Express Standard v1.1, and open-drain current-steering differential outputs 2 compliant to DVI v1.0 and HDMI v1.4b electrical specifications. The I C-bus channel actively buffers as well as level-translates the DDC signals. The PTN3366 supports standby mode in order to minimize current consumption when Hot Plug Detect signal HPD SINK is LOW. PTN3366 is powered from a single 3.3 V power supply consuming a small amount of power (72 mW typical) and is offered in a 32-terminal HVQFN32 package. PTN3366 NXP Semiconductors Low power HDMI/DVI level shifter supporting 3 Gbit/s operation MULTI-MODE DISPLAY SOURCE OE N PTN3366 reconfigurable I/Os DP PHY ELECTRICAL AC-coupled OUT D4+ TMDS DP differential pair OUT D4 output buffer coded TMDS data TX data IN D4+ FF DATA LANE IN D4 TX AC-coupled OUT D3+ TMDS DP differential pair OUT D3 output buffer coded TMDS data TX data IN D3+ FF DATA LANE IN D3 TX AC-coupled OUT D2+ DP TMDS differential pair OUT D2 output buffer coded TMDS data TX data IN D2+ DATA LANE FF IN D2 TX OUT D1+ AC-coupled DP TMDS differential pair OUT D1 clock output buffer clock TX IN D1+ pattern CLOCK LANE FF IN D1 TX 0 V to 3.3 V 0 V to 5 V HPD SOURCE HPD SINK binary inputs EQ0/EQ1 3.3 V DDC EN 3.3 V 5 V SCL SOURCE SCL SINK 3.3 V 5 V DDC I/O 2 (I C-bus) CONFIGURATION SDA SOURCE SDA SINK 002aah583 Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to IN D 4:1 . Fig 1. Typical HDMI/DVI level shifter application system diagram PTN3366 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 1.1 22 May 2015 2 of 26 DVI/HDMI CONNECTOR