NX3P191 Logic controlled high-side power switch Rev. 5 14 January 2014 Product data sheet 1. General description The NX3P191 is a high-side load switch which features a low ON resistance P-channel MOSFET. It has input inrush current reduction that supports more than 500 mA of continuous current. It also has an integrated output discharge resistor to discharge the output capacitance when disabled. Designed for operation from 1.1 V to 3.6 V, it is used in power domain isolation applications to reduce power dissipation and extend battery life. The enable logic includes integrated logic level translation making the device compatible with lower voltage processors and controllers. The NX3P191 is ideal for portable, battery operated applications due to low ground current and ultra-low shutdown current. 2. Features and benefits Wide supply voltage range from 1.1 V to 3.6 V Very low ON resistance: 95 m (typical) at a supply voltage of 1.8 V High noise immunity Low-power mode when EN is LOW Low ground current (2 A maximum) 1.2 V control logic at a supply voltage of 3.6 V High current handling capability (500 mA continuous current) Internal output discharge resistor Turn-on slew rate limiting ESD protection: HBM JESD22-A114F Class 3A exceeds 4000 V CDM AEC-Q100-011 revision B exceeds 500 V Specified from 40 C to +85 C 3. Applications Cell phone Digital cameras and audio devices Portable and battery-powered equipmentNX3P191 NXP Semiconductors Logic controlled high-side power switch 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version NX3P191UK 40 C to +85 C WLCSP4 wafer level chip-size package 4 bumps body NX3P190/NX3P191 0.76 0.76 0.51 mm. (Backside Coating included) 5. Marking Table 2. Marking codes Type number Marking code NX3P191UK x1 6. Functional diagram VIN VOUT R dch LEVEL SHIFT, EN SLEW RATE CONTROL AND LOAD DISCHARGE EN R pd VIN VOUT 001aao342 aaa-000036 Fig 1. Logic symbol Fig 2. Logic diagram (simplified schematic) 7. Pinning information 7.1 Pinning bump A1 NX3P191 index area 12 12 A A VIN VOUT B B EN GND aaa-000037 001aao345 Transparent top view Transparent top view Fig 3. Pin configuration for WLCSP4 Fig 4. Ball mapping for WLCSP4 NX3P191 All information provided in this document is subject to legal disclaimers. NXP B.V. 2014. All rights reserved. Product data sheet Rev. 5 14 January 2014 2 of 15