INTEGRATED CIRCUITS
74F240
Octal inverting buffer (3-state)
Product data 2004 Feb 25
Supersedes data of 2002 Mar 18
Philips Semiconductors Product data
Octal inverting buffer 74F240
FEATURES DESCRIPTION
The 74F240 is an octal inverting buffer that is ideal for driving bus
Octal bus interface
lines of buffer memory address registers. The outputs are all
3-state buffer outputs sink 64 mA
capable of sinking 64 mA and sourcing up to 15 mA. The device
features two output enables, each controlling four of the 3-state
15 mA source current
outputs.
TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL)
74F240 4.3 ns 37 mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE PKG DWG #
V = 5 V 10%, T = 0 C to +70 C
CC amb
20-pin plastic DIP N74F240N SOT146-1
20-pin plastic SOL N74F240D SOT163-1
20-pin plastic SSOP II N74F240DB SOT339-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
74F (U.L.) LOAD VALUE
PINS DESCRIPTION
HIGH/LOW HIGH/LOW
Ian, Ibn Data inputs 1.0/1.67 20 A/1.0 mA
OEa, OEb Output enable inputs (Active-LOW) 1.0/0.33 20 A/0.2 mA
Yan, Ybn Data outputs 750/106.7 15 mA/64 mA
Note to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20 A in the HIGH state and 0.6 mA in the LOW state.
PIN CONFIGURATION LOGIC SYMBOL
OEa 1 20 V
CC
2 4 6 8 17 15 13 11
Ia0 2 19 OEb
Yb0 3 18 Ya0
Ia0 Ia1 Ia2 Ia3 Ib0 Ib1 Ib2 Ib3
Ia1 4 17 Ib0
1 OEa
Yb1 5 16 Ya1
Ia2 6 15 Ib1
19 OEb
Yb2 7 14 Ya2
Ya0 Ya1 Ya2 Ya3 Yb0 Yb1 Yb2 Yb3
Ia3 8 13 Ib2
Yb3 9 12 Ya3
18 16 14 12 3579
GND 10 11 Ib3
V = Pin 20
CC
GND = Pin 10
SF00320
SF00321
2
2004 Feb 25