Document Number: MC33800 Freescale Semiconductor Rev. 5.0, 10/2007 Advance Information Engine Control Integrated Circuit 33800 The 33800 is a combination output switch and driver Integrated Circuit (IC) which can be used in numerous powertrain applications. The IC contains two programmable constant current drivers (CCD), ENGINE CONTROL an octal, low side, serial switch (OSS), and six, external MOSFET gate pre-drivers (GD). The IC has over-voltage, under-voltage, and thermal protection. All drivers and switches, including the external MOSFETs, have over-current protection, off-state open load detection, on-state shorted load detection, and fault annunciation via the serial peripheral interface (SPI). Additional features include: Low power Sleep Mode, Heated Exhaust Gas Oxygen (HEGO) sensor diagnostics, output control via EK SUFFIX (Pb-FREE) serial and/or parallel inputs, PWM capability, and programmable 98ASA99334D current output with dithering. These features, along with cost effective 54-PIN SOICW-EP packaging, make the 33800 ideal for Powertrain Engine Control applications. ORDERING INFORMATION Features Temperature Wide operating voltage range, 5 < VPWR < 36V Device Package Range (T ) A Interfaces to 3.3V and 5V microprocessors via SPI protocol Low, Sleep Mode, standby current, typically 10uA. MCZ33800EK/R2 -40C to 125C 54 SOICW EP Internal or external voltage reference Internal oscillator with calibrate capability Measures resistance to monitor HEGO sensors CCDs have programmable current, dither frequency and amplitude OSSs can be paralleled to increase current capability GDs have programmable frequency and duty cycle PWM All outputs controllable via serial and/or parallel inputs Pb-free packaging designated by suffix code EK 33800 V V PWR BAT VPWR CCD1 REC V DD CCD1 OUT MCU VDD V PWR 2.5V VCAL CCD2 REC RI REF CCD2 OUT V REXT BAT MOSI SI V BAT OUT1 SCLK SCLK OUT8 CS CS SO MISO VDSNS1 DEFAULT GD1 EN VSSNS123 AN0 LRFDBK P1,P3,P5,P7 VDSNS6 PWM1 GD6 PWM6 VSSNS456 GND Figure 1. MC33800 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor, Inc., 2007. All rights reserved.INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VPWR, VDD VPWR VDD POR 80A GND Sleep PWR Oscillator VCAL Bandgap V CCD2 OUT DD 15A CCD1 OUT 15A CCD2 Outputs CCD1 Outputs CCD2 REC DEFAULT CCD1 REC 53V EN 100K Gate Control Open/Short 40A P1 + R 15A S CCGND CCGND lLimit P3 15A Outputs 1 to 8 OUT 1 P5 75A 53V 15A to Gate Control P7 OUT 8 Open/Short Logic Control & 15A SPI Interface + R S SI PGND V lLimit DD PGND 15A 15A PGND Predriver1,2,3 CS VDSNS1 SCLK V PWR SO PWM1 Gate Drive Control & GD1 15A Diagnostics PWM2 VSSNS123 15A Predriver4,5,6 PWM3 VDSNS4 15A V PWR Gate Drive PWM4 GD4 Control & Diagnostics 15A VSSNS456 PWM5 15A Differential Amplifier + PWM6 + LRFDBK 15A + VCAL + VCAL REXT RI REF Exposed Pad Figure 2. 33800 Simplified Internal Block Diagram 33800 Analog Integrated Circuit Device Data 2 Freescale Semiconductor