Product Information

NJU3712M-TE2

NJU3712M-TE2 electronic component of Nisshinbo

Datasheet
Serial to Parallel Logic Converters 8bit Srial to Prll

Manufacturer: Nisshinbo
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (AUD)

500: AUD 3.3393 ( AUD 3.67 Inc GST) ea
Line Total: AUD 1669.65 ( AUD 1836.62 Inc GST)

0 - Global Stock
MOQ: 500  Multiples: 500
Pack Size: 500
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 12 Jul to Thu. 18 Jul

MOQ : 500
Multiples : 500

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NJU3712M-TE2
Nisshinbo

500 : AUD 3.3393
1000 : AUD 1.9714
1500 : AUD 1.56
2000 : AUD 1.5257

     
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NJU3712A 8-BIT SERIAL TO PARALLEL CONVERTER GENERAL DESCRIPTION PACKAGE OUTLINE The NJU3712A is an 8-bit serial to parallel converter especially applying to MPU outport expander. It can operate from 2.4V to 5.5V. The effective outport assignment of MPU is available as the connection between NJU3712A and MPU using only 4 lines. The serial data synchronizing with 5MHz or more NJU3712AV clock can be input to the serial data input terminal and the data are output from parallel output buffer through serial in parallel out shift register and parallel data latches. Furthermore, the NJU3712A outputs the serial data from SO terminal through the shift register. Therefore, it connects with other SIPO ICs like as NJU3711A in cascade for expanding the parallel conversion outputs. The hysteresis input circuit realizes wide noise margin and the high drive-ability output buffer (25mA) can drive LED directly. PIN CONFIGURATION FEATURES 8-Bit Serial In Parallel Out V 1 16 DD P3 Cascade Connection P4 2 15 P2 Hysteresis Input 0.5V typ at 5V P1 P5 3 14 Operating Voltage 2.4 to 5.5V V 4 13 V SS SS Maximum Operating Frequency 5MHz 5 12 CLR P6 Output Current 25mA at 5V, 5mA at 3V 11 STB P7 6 P8 CLK 7 10 C-MOS Technology 9 DATA SO 8 Package Outline SSOP16 NJU3712AV BLOCK DIAGRAM P1 DATA P2 CLK P3 P7 P8 SO STB Controller Circuit CLR Ver.2012-03-15 -1- Shift Register Latch Circuit NJU3712A TERMINAL DESCRIPTION No. SYMBOL I/O FUNCTION 1 P3 O Parallel Conversion Data Output Terminals 2 P4 O 3 P5 O 4 V - GND SS 5 P6 O 6 P7 O Parallel Conversion Data Output Terminals 7 P8 O 8 SO O Serial Data Output Terminal 9 DATA I Serial Data Input Terminal 10 CLK I Clock Signal Input Terminal STB 11 I Strobe Signal Input Terminal 12 CLR I Clear Signal Input Terminal 13 V - GND SS 14 P1 O Parallel Conversion Data Output Terminals 15 P2 O 16 V - Power Supply Terminal (2.4 to 5.5V) DD Ver.2012-03-15 - 2 -

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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