74LVC1G3157-Q100 2-channel analog multiplexer/demultiplexer Rev. 5 28 January 2019 Product data sheet 1. General description The 74LVC1G3157-Q100 provides one analog multiplexer/demultiplexer with one digital select input (S), two independent inputs/outputs (Y0, Y1) and a common input/output (Z). Schmitt trigger action at the select input makes the circuit tolerant of slower input rise and fall times across the entire V range from 1.65 V to 5.5 V. CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V Very low ON resistance: 7.5 (typical) at V = 2.7 V CC 6.5 (typical) at V = 3.3 V CC 6 (typical) at V = 5 V CC Switch current capability of 32 mA Break-before-make switching High noise immunity CMOS low power consumption TTL interface compatibility at 3.3 V Latch-up performance meets requirements of JESD 78 Class I Control input accepts voltages up to 5.5 V Multiple package options ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G3157GW-Q100 -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74LVC1G3157GV-Q100 -40 C to +125 C SC-74 plastic surface-mounted package (SC-74 SOT457 TSOP6) 6 leads 74LVC1G3157GM-Q100 -40 C to +125 C XSON6 plastic extremely thin small outline package SOT886 no leads 6 terminals body 1 1.45 0.5 mmNexperia 74LVC1G3157-Q100 2-channel analog multiplexer/demultiplexer 4. Marking Table 2. Marking Type number Marking code 1 74LVC1G3157GW-Q100 YJ 74LVC1G3157GV-Q100 YJ 74LVC1G3157GM-Q100 YJ 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Y1 S Z S 6 1 Y1 Z 4 Y0 3 Y0 001aac354 001aac355 Fig. 1. Logic symbol Fig. 2. Logic diagram 6. Pinning information 6.1. Pinning 74LVC1G3157 74LVC1G3157 Y1 1 6 S Y1 1 6 S GND 2 5 V CC GND 2 5 V CC Y0 3 4 Z Y0 3 4 Z Transparent top view 001aac356 001aac357 Fig. 3. Pin configuration SOT363 (SC-88) and SOT457 (SC-74) Fig. 4. Pin configuration SOT886 (XSON6) 74LVC1G3157 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 5 28 January 2019 2 / 18