74LVC1G175-Q100 Single D-type flip-flop with reset positive-edge trigger Rev. 3 3 October 2019 Product data sheet 1. General description The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using I . The I circuitry disables the output, preventing the OFF OFF damaging backflow current through the device when it is powered down. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V). 24 mA output drive (V = 3.0 V) CC CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 ) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G175GW-Q100 -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74LVC1G175GV-Q100 -40 C to +125 C SC-74 plastic surface-mounted package SOT457 (SC-74 TSOP6) 6 leadsNexperia 74LVC1G175-Q100 Single D-type flip-flop with reset positive-edge trigger 4. Marking Table 2. Marking Type number Marking code 1 74LVC1G175GW-Q100 YT 74LVC1G175GV-Q100 V75 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 6 MR 3 1 D CP 4 FF 3 Q 4 D Q 1 CP 6 MR 001aaa468 001aaa469 Fig. 1. Logic symbol Fig. 2. IEC logic symbol CP C Q C C C C C C C D C C MR 001aaa466 Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74LVC1G175-Q100 CP 1 6 MR GND 2 5 V CC D 3 4 Q aaa-009630 Fig. 4. Pin configuration SOT363 (SC-88) and SOT457 (SC-74) 74LVC1G175 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 3 3 October 2019 2 / 13