74LV165PW,118

74LV165 8-bit parallel-in/serial-out shift register Rev. 8 21 September 2021 Product data sheet 1. General description The 74LV165 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess V . CC 2. Features and benefits Wide supply voltage range from 1.0 to 5.5 V CMOS low power dissipation Direct interface with TTL levels (2.7 V to 3.6 V) Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Optimized for low voltage applications: 1.0 V to 3.6 V Synchronous parallel-to-serial applications Synchronous serial input for easy expansion Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV165D -40 C to +125 C SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1 74LV165PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mmNexperia 74LV165 8-bit parallel-in/serial-out shift register 4. Functional diagram SRG8 1 C2 LOAD G1 SHIFT 15 1 10 C3/ 1 2 DS 11 D0 10 3D 12 D1 11 13 2D D2 12 14 2D D3 13 3 D4 14 4 D5 3 5 9 D6 Q7 4 6 7 D7 Q7 1 5 PL 9 6 CP CE 7 2 15 mna985 aaa-008827 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 11 12 13 14 3 4 5 6 D0 D1 D2 D3 D4 D5 D6 D7 1 PL 10 DS Q7 9 8-BIT SHIFT REGISTER 2 CP PARALLEL-IN/SERIAL-OUT Q7 7 15 CE aaa-008826 Fig. 3. Functional diagram D0 D1 D2 D3 D4 D5 D6 D7 DS SD SD SD SD SD SD SD SD CP D Q D Q D Q D Q D Q D Q D Q D Q Q7 CP CP CP CP CP CP CP CP FF0 FF1 FF2 FF3 FF4 FF5 FF6 FF7 CE Q Q7 RD RD RD RD RD RD RD RD PL aaa-008828 Fig. 4. Logic diagram 74LV165 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 21 September 2021 2 / 16