74HC595-Q100 74HCT595-Q100 8-bit serial-in, serial or parallel-out shift register with output latches 3-state Rev. 4 11 March 2020 Product data sheet 1. General description The 74HC595-Q100 74HCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C 8-bit serial input 8-bit serial or parallel output Storage register with 3-state outputs Shift register with direct clear 100 MHz (typical) shift out frequency Complies with JEDEC standard no. 7A Input levels: For 74HC595-Q100: CMOS level For 74HCT595-Q100: TTL level ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Applications Serial-to-parallel data conversion Remote control holding registerNexperia 74HC595-Q100 74HCT595-Q100 8-bit serial-in, serial or parallel-out shift register with output latches 3-state 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC595D-Q100 -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT595D-Q100 74HC595PW-Q100 -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT595PW-Q100 74HC595BQ-Q100 -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal SOT763-1 enhanced very thin quad flat package no leads 74HCT595BQ-Q100 16 terminals body 2.5 3.5 0.85 mm 5. Functional diagram 14 DS 11 SHCP 8-STAGE SHIFT REGISTER 10 MR Q7S 9 12 STCP 8-BIT STORAGE REGISTER 13 OE 3-STATE OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 15 1 2 3 4 5 6 7 mna554 Fig. 1. Functional diagram 13 EN3 12 C2 11 12 10 SHCP STCP SRG8 R 11 9 C1/ Q7S 15 Q0 14 15 1D 2D 3 1 Q1 1 2 Q2 2 14 3 Q3 DS 3 4 Q4 4 5 Q5 5 6 Q6 6 7 Q7 7 MR OE 9 10 13 mna552 mna553 Fig. 2. Logic symbol Fig. 3. IEC logic symbol 74HC HCT595 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 4 11 March 2020 2 / 20