74CBTLV3125 4-bit bus switch Rev. 6 23 September 2020 Product data sheet 1. General description The 74CBTLV3125 provides a 4-bit high-speed bus switch with separate output enable inputs (1OE to 4OE). The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The switch is disabled (high-impedance OFF-state) when the output enable (nOE) input is HIGH. To ensure the high-impedance OFF-state during power-up or power-down, nOE should be tied to the V through a pull-up resistor. The minimum value of the resistor is determined by the CC current-sinking capability of the driver. Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire V range from 2.3 V to 3.6 V. CC This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits Supply voltage range from 2.3 V to 3.6 V High noise immunity Complies with JEDEC standard: JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM AEC-Q100-011 revision B exceeds 1000 V 5 switch connection between two ports Rail to rail switching on data I/O ports CMOS low power consumption Latch-up performance exceeds 250 mA per JESD78B Class I level A I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from -40 C to +85 C and -40 C to +125 CNexperia 74CBTLV3125 4-bit bus switch 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74CBTLV3125DS -40 C to +125 C SSOP16 1 plastic shrink small outline package 16 leads SOT519-1 body width 3.9 mm lead pitch 0.635 mm 74CBTLV3125PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74CBTLV3125BQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mm 1 Also known as QSOP16. 4. Functional diagram 1OE 1A 1B 2OE 2A 2B 3OE 3A 3B nA nB 4OE 4A 4B nOE 001aak863 001aak856 Fig. 1. Logic symbol Fig. 2. Logic diagram (one switch) 74CBTLV3125 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 23 September 2020 2 / 17