UXD20K DC-26.5 GHz Programmable 1,2,4,8 Binary Prescaler Application Features The UXD20K can be used as a general Wide Operating Range: DC-26.5 purpose, fixed modulus prescaler in high GHz frequency PLLs. The low phase noise of the Low SSB Phase Noise: -153 dBc divider makes it ideal for generating low jitter, 10 kHz synchronous clocks in telecom applications. Large Output Swings: 750 mV ppk/ side Pad Metallization Single-Ended and/or Differential The QFN package pad metallization consists Operation of a 500-1000 micro-inch Sn63 automated Low power consumption: 430 mW solder dip process. 4x4 ceramic leadless QFN package 3 Dividers-in-One with Pass Through DC-7 GHz Limit Amp Description The UXD20K is a low noise DC to 26.5 GHz programmable prescaler featuring either divide by-1, divide-by-2, divide-by-4, or divide-by-8 division ra- tios. In the divide by 1 mode the UX- D20K is also a limit amplifier. The device features differential inputs and outputs, adjustable output swing and high input sensitivity. The control inputs are CMOS and LVTTL compat- ible. The UXD20K is packaged in a 24 pin, 4 mm x 4 mm ceramic leadless surface mount package. Key Specifications (T = 25C): Vee = -3.3 V, Iee = 130 mA, Zo=50 Parameter Description Min Typ Max Fin (GHz) Input Frequency DC* - 26.5 Pin (dBm) Input Power -10 0 10 Pout (dBm) Output Power -5 5 - (dBc/Hz) SSB Phase Noise 10 kHz Offset - -153 - PDC (mW) DC Power Dissipation - 430 - jc (C/W) Junction-Case Thermal Resistance - 52 - * Low frequency limit dependent on input edge speed SMD-00091 Rev F 1 of 9 Subject to Change Without Notice UXD20K Frequency Divider Application Min/Max Single-Ended Input Power Binary Divide-by-2 Output Power, 3rd Harmonic & Input Feedthru Input Sensitivity Window UXD20K: SSB Phase Noise for Binary Divide-by-8 Configuration Input Freq = 7.8 GHz Gain S21 SMD-00091 Rev F 2 of 9 Subject to Change Without Notice