SY89874U 2.5GHz, Any Differential, In-to-LVPECL, Programmable Clock Divider/Fanout Buffer with Internal Termination General Description This low-skew, low-jitter device is capable of accepting a Precision Edge high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the Features frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. Integrated programmable clock divider and 1:2 fanout buffer Available divider ratios are 2, 4, 8 and 16, or straight pass- through. In a typical 622MHz clock system this would Guaranteed AC performance over temperature and provide availability of 311MHz, 155MHz, 77MHz, or voltage: 38MHz auxiliary clock components. >2.5GHz f MAX The differential input buffer has a unique internal <250ps t /t r f termination design that allows access to the termination <15ps within-device skew network through a V pin. This feature allows the device to T Low-jitter design: easily interface to different logic standards. A V REF-AC <10ps total jitter PP reference is included for AC-coupled applications. <1ps cycle-to-cycle jitter RMS The /RESET input asynchronously resets the divider. In Unique input termination and VT pin for DC-coupled and the pass-through function (divide by 1) the /RESET AC-coupled Inputs CML, PECL, LVDS, and HSTL synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N). TTL/CMOS inputs for select and reset 100k EP-compatible LVPECL outputs Datasheets and support documentation are available on Parallel programming capability Micrels web site at: www.micrel.com. Programmable divider ratios of 1, 2, 4, 8 and 16 Low-voltage operation 2.5V or 3.3V Output disable function 40C to 85C temperature range Available in 16-pin (3mm x 3mm) QFN package Applications SONET/SDH line cards Transponders High-end multiprocessor sensors PrecisionEdge is a registered trademark of Micrel, Inc. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. SY89874U Ordering Information (1) Part Number Package Type Operating Range Package Marking Lead Finish 874U with Pb-free SY89874UMG QFN-16 Industrial NiPdAu bar-line indicator 874U with Pb-free (2) SY89874UMGTR QFN-16 Industrial NiPdAu bar-line indicator Note: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. Pin Configuration 16-Pin QFN Pin Description Pin Number Pin Name Pin Function Differential input. Internal 50 termination resistors to VT input. Flexible input accepts any 12, 9 IN, /IN differential input. See the Input Interface Applications section. Q0, /Q0 Differential buffered LVPECL Outputs. Divided by 1, 2, 4, 8, or 16. See Truth Table. Unused 1, 2, 3, 4 Q1, /Q1 PECL outputs may be left floating with no impact on jitter performance. Select pins. See Truth Table. LVTTL/CMOS logic levels. Internal 25k pull-up resistor. Logic 16, 15, 5 S0, S1, S2 HIGH if left unconnected (divided by 16 mode). Input threshold is V /2. CC 6 NC No connect. LVTTL/CMOS logic levels. Internal 25k pull-up resistor. Logic HIGH if left unconnected. Apply /RESET LOW to reset the divider (divided by 2, 4, 8, or 16 mode). Also acts as a synchronous 8 /DISABLE disable/enable function. The reset and disable function occurs on the next HIGH-to-LOW clock input transition. Input threshold is V /2. CC Reference voltage. Equal to V -1.4V (approximately). Used for AC-coupled applications only. CC 10 VREF-AC Decouple the VREF-AC pin with a 0.01F capacitor. See the Input Interface Applications section. Termination center tap. For CML or LVDS inputs, leave this floating. Otherwise, see Figures 2a to 11 VT 2f within the Input Interface Applications section. 7, 14 VCC Positive power supply. Bypass with .01F /0.01F low-ESR capacitor. 13 GND Ground. Revision 1.1 October 1, 2013 2 hbwhelp micrel.com or (408) 955-1690