Product Information

SY89871UMG-TR

SY89871UMG-TR electronic component of Microchip

Datasheet
Clock Drivers & Distribution 2.5V/3.3V PECL Output Clock Divider/Fanout

Manufacturer: Microchip
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (AUD)

1: AUD 20.2754 ( AUD 22.3 Inc GST) ea
Line Total: AUD 20.2754 ( AUD 22.3 Inc GST)

1090 - Global Stock
Ships to you between
Thu. 18 Jul to Mon. 22 Jul
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
896 - Global Stock


Ships to you between Thu. 18 Jul to Mon. 22 Jul

MOQ : 1
Multiples : 1

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SY89871UMG-TR
Microchip

1 : AUD 20.2754
100 : AUD 17.3562
500 : AUD 15.7992

     
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SY89871U 2.5GHz Any Diff. In-To-LVPECL Programmable Clock Divider/Fanout Buffer w/ Internal Termination Precision Edge General Description Features The SY89871U is a 2.5V/3.3V LVPECL output precision Two matched-delay outputs: clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or - Bank A: undivided pass-through (QA) - Bank B: programmable divide by 2, 4, 8, 16 (QB0, LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency- QB1) locked lower speed version of the input clock (Bank B). Matched delay: all outputs have matched delay, Available divider ratios are 2, 4, 8, and 16. In a typical independent of divider setting 622MHz clock system this would provide availability of Guaranteed AC performance: 311MHz, 115MHz, 77MHz, or 38MHz auxiliary clock - >2.5GHz f MAX components. - <250ps t /t r f The differential input buffer has a unique internal - <670ps t (matched delay) pd termination design that allows access to the termination - <15ps within-device skew network through a VT pin. This feature allows the device to Low jitter design easily interface to different logic standards. A V REF-AC - 231fs RMS phase jitter (Typ) reference is included for AC-coupled applications. Power supply 3.3V or 2.5V The SY89871U includes two phase-matched output banks. Unique patent-pending input termination and VT pin for Bank A (QA) is a frequency-matched copy of the input. DC- and AC- coupled inputs: any differential inputs Bank B (QB0, QB1) is a divided down output of the input (LVPECL, LVDS, CML, HSTL) frequency. Bank A and Bank B maintain a matched delay TTL/CMOS inputs for select and reset independent of the divider setting. 100K EP compatible LVPECL outputs Data sheets and support documentation can be found on Micrels web site at: www.micrel.com. Parallel programming capability Wide operating temperature range: -40C to +85C Available in 16-pin (3mm x 3mm) QFN package Typical Performance Applications OC-3 to OC-192 SONET/SDH applications Transponders Oscillators SONET/SDH line cards United States Patent No. RE44,134 Precision Edge is a registered trademark of Micrel, Inc Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Functional Block Diagram Ordering Information Part Number Package Type Operating Range Package Marking Lead Finish (2) SY89871UMG QFN-16 Industrial 871U with Pb-Free bar line indicator NiPdAu Pb-Free (1,2) SY89871UMGTR QFN-16 Industrial 871U with Pb-Free bar line indicator NiPdAu Pb-Free Note: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. Oct. 1, 2013 2 M9999-010512-F hbwhelp micrel.com or (408) 955-1690

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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