SY89833L 3.3V Ultra-Precision 1:4 LVDS Fanout Buffer/Translator with Internal Termination Features General Description Guaranteed AC Performance Over Temperature The SY89833L is a 3.3V, high-speed 2 GHz differential, and Voltage: low voltage differential swing (LVDS) 1:4 fanout buffer optimized for ultra-low skew applications. Within device - DC-to > 2 GHz throughput skew is guaranteed to be less than 20 ps over supply - <600 ps Propagation Delay (IN-to-Q) voltage and temperature. - <20 ps Within-Device Skew The differential input buffer has a unique internal - <190 ps Rise/Fall Times termination design that allows access to the Ultra-Low Jitter Design: termination network through a V pin. This feature T - 96 fs Additive Phase Jitter (typical) RMS allows the device to easily interface to different logic Patented Any-In Input Termination and V Pin reference is included for standards. A V T REF-AC Accepts DC- and AC-Coupled Inputs AC-coupled applications. High-Speed LVDS Outputs The SY89833L is part of Microchips high-speed clock 3.3V Power Supply Operation synchronization family. For 2.5V applications, the SY89832U provides similar functionality while Industrial Temperature Range: 40C to +85C operating from a 2.5V 5% supply. For applications that Available in 16-Pin (3mm 3mm) VQFN Package require a different I/O combination, consult the Applications Microchip website and choose from a comprehensive product line of high-speed, low-skew fanout buffers, Processor Clock Distribution translators, and clock generators. SONET Clock Distribution Fibre Channel Clock Distribution Gigabit Ethernet Clock Distribution Package Type SY89833L 3x3 VQFN (M) 16 15 14 13 1 12 Q1 IN /Q1 2 11 VT 3 10 VREF-AC Q2 4 /Q2 9 /IN 5 6 7 8 United States Patent No. RE44,134 2021 Microchip Technology Inc. DS20005726A-page 1 Q3 /Q0 /Q3 Q0 VCC VCC EN GNDSY89833L Functional Block Diagram 1:4 Q0 /Q0 Q1 IN /Q1 50 VT 50 /IN Q2 VREF-AC /Q2 EN DQ (LVTTL/CMOS) Q3 /Q3 DS20005726A-page 2 2021 Microchip Technology Inc.