Product Information

PM8532B-F3EI

PM8532B-F3EI electronic component of Microchip

Datasheet
PCI Interface IC Switchtec Gen 3 32 Lanes 16 Ports

Manufacturer: Microchip
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Price (AUD)

1: AUD 351.0913 ( AUD 386.2 Inc GST) ea
Line Total: AUD 351.0913 ( AUD 386.2 Inc GST)

97 - Global Stock
Ships to you between
Thu. 18 Jul to Mon. 22 Jul
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
39 - Global Stock


Ships to you between Thu. 18 Jul to Mon. 22 Jul

MOQ : 1
Multiples : 1

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PM8532B-F3EI
Microchip

1 : AUD 313.0654
120 : AUD 285.0585
520 : AUD 275.4162

     
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Switchtec PCIe Switches Switchtec PFX/PFX-I PCIe Gen3 Fanout Switch Families PM853x PFX and PM857x PFX-I 96/80/64/48/32/24xG3 PCIe Gen3 Fanout Switches Summary The Switchtec PFX/PFX-I PCIe Gen3 fanout switch families comprise high reliabil- ity PCIe Base Specifi cation 3.1-compliant switches supporting up to 96 lanes, 24 virtual switch partitions, 48 Non-Transparent Bridges (NTBs), hot- and surprise- plug controllers for each port, advanced error containment and comprehensive diagnostics and debug capabilities. The PFX-I Gen3 PCIe Switch supports the full feature set available on the PFX* and operates over an extended industrial temperature range of 40C ambient to 105C junction. Typical applications include data center equipment, defense, industrial servers, workstations, test equipment, video production and broadcasting equipment, cellular infrastructure, access networks, metro networks and core networking. Features High-Performance Non-Blocking Switches PCIe Interfaces Up to 174 GB/s switching capacity Passive, managed and optical cables 96-lane, 80-lane, 64-lane, 48-lane, 32-lane, and 24-lane SFF-8644, SFF-8643, SFF-8639, OCuLink and other variants connectors Ports bifurcate from x2 to x16 lanes SHPC-enabled slot and edge connectors Up to 48 NTBs assignable to any port Diagnostics and Debug Logical Non-Transparent (NT) interconnect allows for larger Transaction Layer Packet (TLP) generator for testing and topologies (up to 256 masters) debugging of links and error handling Supports 1+1 and N+1 failover mechanisms Real-time eye capture NT address translation using direct windows and multiple Any-to-any port mirroring for debug purposes sub-windows per BAR External loopback at PHY and TLP layers Supports multicast groups per port Errors, statistics, performance, and TLP latency counters PFX-I supports an extended industrial temperature range T : 40C to T : 105C A J Error Containment Advanced Error Reporting (AER) on all ports Downstream Port Containment (DPC) on all downstream ports Poisoned TLP blocking Completion Timeout Synthesis (CTS) to prevent an error state in an upstream host due to incomplete non-posted transactions Hot- and surprise-plug controllers per port GPIOs confi gurable for di erent cable/connector standards *Except for Adaptive Voltage Scaling (AVS) www.microchip.comPower Management Highlights Active State Power Management (ASPM) High-reliability PCIe: robust error containment, hot- and Software controlled power management surprise-plug controllers per port, end-to-end data integrity protection, ECC protection on RAMs, high-quality, low- Chiplink Diagnostic Tools power SERDES Extensive debug, diagnostics, configuration and analysis Comprehensive diagnostics and debugging: PCIe genera- tools with an intuitive GUI tor and analyzer, per-port performance and error counters, Access to configuration data, management capabilities multiple loopback modes and real-time eye capture and signal integrity analysis tools (such as real-time eye Significant power, cost and boar d space savings with capture) support for: Connects to device over in-band PCIe or sideband signals Up to 48 ports, 48 NTBs and 24 virtual switch parti- (UART, TWI and EJTAG) tions Flexible x2, x4, x8 and x16 port bifurcation with no Evaluation Kit restrictions on configuring ports as either upstream or The evaluation kit is a device evaluation environment support- downstream or on mapping ports to NTBs ing multiple host and SSD interfaces. These kits can be used Peripheral I/O Interfaces for evaluation of the Switchtec PCIe Fanout switches. Note that a 96-lane PCIe switch is populated on the evaluation kit. Up to 11 Two-Wire Interfaces (TWIs) with SMBus support The following kit is available: Up to 2 SFF-8485-compliant SGPIO ports PM5461-KIT - PAX/PSX/PFX/PFX-I/PFX-L 96/80/64G3 Up to 109 parallel GPIO pins PCIe Switch HD Evaluation Kit (PMC-2151996) Up to 4 UARTs JTAG and EJTAG interface Example Application High-Speed I/O PCIe Gen3 8 GT/s Host Host Supports PCIe-compliant link training and manual PHY configuration x16 x16 NVMe SSD PFX 96xG3 PFX 96xG3 NVMe PM8536 PM8536 SSD NVMe x2/x4 SSD x2/x4 Ordering Information Hot-plug Product Lanes Ports/NTBs Partitions Package PFX Ordering No. PFX-I Ordering No. Controllers 96xG3 PCIe Fanout Switch 96 48 24 48 37.5 mm x 37.5 mm PM8536B-FEI PM8576B-FEI 80xG3 PCIe Fanout Switch 80 40 20 40 37.5 mm x 37.5 mm PM8535B-FEI PM8575B-FEI 64 32 16 32 37.5 mm x 37.5 mm PM8534B-FEI PM8574B-FEI 64xG3 PCIe Fanout Switch 48xG3 PCIe Fanout Switch 48 24 12 24 27.0 mm x 27.0 mm PM8533B-F3EI PM8573B-F3EI 32xG3 PCIe Fanout Switch 32 16 8 16 27.0 mm x 27.0 mm PM8532B-F3EI PM8572B-F3EI 24xG3 PCIe Fanout Switch 24 12 6 12 27.0 mm x 27.0 mm PM8531B-F3EI PM8571B-F3EI The Microchip name and logo and the Microchip logo are registered trademarks and Switchtec is a trademark of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks mentioned herein are property of their respective companies. 2019, Microchip Technology Incorporated. All Rights Reserved. 2/19 DS00002849B www.microchip.com

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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