KSZ8795CLX Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/ RMII Interfaces - Target Applications - 802.1az EEE Supported Industrial Ethernet Applications that Employ IEEE - On-Chip Termination Resistors and Internal 802.3-Compliant MACs. (Ethernet/IP, Profinet, Biasing for Differential Pairs to Reduce MODBUS TCP, etc.) Power VoIP Phone - HP Auto MDI/MDI-X Crossover Support Elim- Set-Top/Game Box inates the Need to Differentiate Between Straight or Crossover Cables in Applications Automotive MAC and GMAC Ports Industrial Control - Four Internal Media Access Control (MAC1 to IPTV POF MAC4) Units and One Internal Gigabit Media SOHO Residential Gateway with Full-Wire Speed Access Control (GMAC5) Unit of Four LAN Ports - GMII, RGMII, MII or RMII Interfaces Support Broadband Gateway/Firewall/VPN for the Port 5 GMAC5 with Uplink Integrated DSL/Cable Modem - 2 KByte Jumbo Packet Support Wireless LAN Access Point + Gateway - Tail Tagging Mode (One Byte Added Before Standalone 10/100 Switch FCS) Support on Port 5 to Inform the Proces- Networked Measurement and Control Systems sor in which the Ingress Port Receives the Packet and its Priority Features - Supports Reduced Media Independent Inter- face (RMII) with 50 MHz Reference Clock Management Capabilities Output - The KSZ8795CLX Includes All the Functions - Supports Media Independent Interface (MII) of a 10/100BASE-T/TX Switch System Which in Either PHY Mode or MAC Mode on Port 5 Combines a Switch Engine, Frame Buffer - LinkMD Cable Diagnostic Capabilities for Management, Address Look-Up Table, Determining Cable Opens, Shorts, and Queue Management, MIB Counters, Media Length Access Controllers (MAC), and PHY Trans- ceivers Advanced Switch Capabilities - Non-Blocking Store-and-Forward Switch - Non-Blocking Store-and-Forward Switch Fabric Assures Fast Packet Delivery by Uti- Fabric Assures Fast Packet Delivery by Uti- lizing 1024 Entry Forwarding Table lizing a 1024-Entries Forwarding Table - Port Mirroring/Monitoring/Sniffing: Ingress - 64 KB Frame Buffer RAM and/or Egress Traffic to Any Port - IEEE 802.1q VLAN Support for up to 128 - MIB Counters for Fully-Compliant Statistics Active VLAN Groups (Full-Range 4096 of VLAN IDs) Gathering (36 Counters per Port) - Support Hardware for Port-Based Flush and - IEEE 802.1p/Q Tag Insertion or Removal on a Per Port Basis (Egress) Freeze Command in MIB Counter. - Multiple Loopback of Remote, PHY, and MAC - VLAN ID Tag/Untag Options on Per Port Basis Modes Support for the Diagnostics - Fully Compliant with IEEE 802.3/802.3u - Rapid Spanning Tree Support (RSTP) for Standards Topology Management and Ring/Linear Recovery - IEEE 802.3x Full-Duplex with Force-Mode Option and Half-Duplex Back-Pressure Colli- Robust PHY Ports sion Flow Control - Four Integrated IEEE 802.3/802.3u-Compli- - IEEE 802.1w Rapid Spanning Tree Protocol ant Ethernet Transceivers Supporting Support 10BASE-T and 100BASE-TX 2016-2021 Microchip Technology Inc. DS00002112D-page 1KSZ8795CLX - IGMP v1/v2/v3 Snooping for Multicast Packet - Supports IEEE P802.3az Energy Efficient Filtering Ethernet (EEE) to Reduce Power Consump- tion in Transceivers in LPI State Even - QoS/CoS Packets Prioritization Support: Though Cables are Not Removed 802.1p, DiffServ-Based and Re-Mapping of 802.1p Priority Field Per Port Basis on Four - Dynamic Clock Tree Control to Reduce Priority Levels Clocking in Areas that are Not in Use - IPv4/IPv6 QoS Support - Low Power Consumption without Extra Power Consumption on Transformers - IPV6 Multicast Listener Discovery (MLD) Snooping - Voltages: Using External LDO Power Sup- plies - Programmable Rate Limiting at the Ingress and Egress Ports on a Per Port Basis - Analog V 3.3V or 2.5V DDAT - Jitter-Free Per Packet Based Rate Limiting -V Support 3.3V, 2.5V, and 1.8V DDIO Support - Low 1.2V Voltage for Analog and Digital Core - Tail Tag Mode (1 byte Added before FCS) Power Support on Port 5 to Inform the Processor - WoL Support with Configurable Packet Con- which Ingress Port Receives the Packet trol - Broadcast Storm Protection with Percentage Additional Features Control (Global and Per Port Basis) - Single 25 MHz +50 ppm Reference Clock - 1K Entry Forwarding Table with 64 KB Frame Requirement Buffer - Comprehensive Programmable Two-LED - 4 Priority Queues with Dynamic Packet Map- Indicator Support for Link, Activity, Full-/Half- ping for IEEE 802.1P, IPV4 TOS (DIFF- Duplex, and 10/100 Speed SERV), IPv6 Traffic Class, etc. Packaging and Environmental - Supports WoL Using AMDs Magic Packet - Commercial Temperature Range: 0C to - VLAN and Address Filtering +70C - Supports 802.1x Port-Based Security, - Industrial Temperature Range: 40C to Authentication and MAC-Based Authentica- +85C tion via Access Control Lists (ACL) - Package Available in an 80-Pin LQFP, Lead- - Provides Port-Based and Rule-Based ACLs Free (RoHS-Compliant) Package to Support Layer 2 MAC SA/DA Address, - Supports Human Body Model (HBM) ESD Layer 3 IP Address and IP Mask, Layer 4 Rating of 5 kV TCP/UDP Port Number, IP Protocol, TCP - 0.065 m CMOS Technology for Lower Flag and Compensation for the Port Security Power Consumption Filtering - Ingress and Egress Rate Limit Based on Bit per Second (bps) and Packet-Based Rate Limiting (pps) Configuration Registers Access - High-Speed SPI (4-Wire, up to 25 MHz) Inter- face to Access All Internal Registers - MII Management (MIIM, MDC/MDIO 2-Wire) Interface to Access All PHY Registers per Clause 22.2.4.5 of the IEEE 802.3 Specifica- tion - I/O Pin Strapping Facility to Set Certain Reg- ister Bits from I/O Pins During Reset Time - Control Registers Configurable On-the-Fly Power and Power Management - Full-Chip Software Power-Down (All Register Values are Not Saved and Strap-In value Will Re-Strap after it Releases the Power-Down) - Per-Port Software Power-Down - Energy Detect Power-Down (EDPD), which Disables the PHY Transceiver When Cables are Removed 2016-2021 Microchip Technology Inc. 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