This is a summary document. A complete document is available under NDA. For more information, please contact your local Microchip sales office. ATECC608B CryptoAuthentication Device Summary Data Sheet Features Cryptographic Co-Processor with Secure Hardware-Based Key Storage: Protected storage for up to 16 keys, certificates or data Hardware Support for Asymmetric Sign, Verify, Key Agreement: ECDSA: FIPS186-3 Elliptic Curve Digital Signature ECDH: FIPS SP800-56A Elliptic Curve Diffie-Hellman NIST Standard P256 (ECC secp256r1) Elliptic Curve Support Hardware Support for Symmetric Algorithms: SHA-256 & HMAC Hash including off-chip context save/restore AES-128: Encrypt/Decrypt, Galois Field Multiply for GCM Networking Key Management Support: Turnkey PRF/HKDF calculation for TLS 1.2 & 1.3 Ephemeral key generation and key agreement in SRAM Small message encryption with keys entirely protected Secure Boot Support: Full ECDSA code signature validation, optional stored digest/signature Optional communication key disablement prior to secure boot Encryption/Authentication for messages to prevent on-board attacks Internal High-Quality NIST SP 800-90A/B/C Random Number Generator (RNG) Two High-Endurance Monotonic Counters Unique 72-Bit Serial Number Two Interface Options Available: High-Speed Single Wire Interface with One GPIO Pin 2 1 MHz Standard I C Interface 1.8V to 5.5V IO Levels, 2.0V to 5.5V Supply Voltage Two Temperature Ranges Available: Standard Industrial Temperature Range: -40 to +85 Extended Industrial Temperature Range: -40 to +100 <150 nA Sleep Current Packaging Options 8-pad UDFN, 8-lead SOIC and 3-Lead Contact Package Options Die-on-Tape and Reel and WLCSP for Qualified Customers (Contact Microchip Sales) Applications IoT network endpoint key management & exchange Encryption for small messages and PII data Secure Boot and Protected Download Ecosystem Control, Anti-cloning Summary Datasheet DS40002239B-page 1 2020-20021 Microchip Technology Inc. and its subsidiaries ATECC608B Pin Configuration and Pinouts Table 1. Pin Configuration 2 Pin Function I C Interface Function SWI Interface NC No Connect No Connect GND Ground Ground SDA Serial Data Serial Data SCL Serial Clock Input GPIO V Power Supply Power Supply CC Figure 1. Package Types 8-lead SOIC 8-pad UDFN 3-lead Contact (Top View) (Top View) (Top View) NC 1 8 VCC NC 1 8 VCC NC 2 7 NC 1 SDA 7 NC 2 NC NC SCL 3 6 NC 3 6 SCL GND SDA 4 5 5 GND 4 SDA 2 GND 3 VCC Note: The UDFN backside paddle is recommended to be connected to GND. DS40002239B-page 2 Summary Datasheet 2020-20021 Microchip Technology Inc. and its subsidiaries