IS62/65WV102416DALL IS62/65WV102416DBLL JANUARY 2015 1Mx16 LOW VOLTAGE, ULTRA LOW POWER & LOW POWER CMOS STATIC RAM KEY FEATURES DESCRIPTION The ISSI IS62/65WV102416DALL, High-speed access time: 45ns, 55ns. IS62/65WV102416DBLL are ULTRA LOW POWER CMOS low power operation CMOS 16Mbit static RAMs organized as 1M words 25 A (typical) CMOS standby by 16 bits. It is fabricated using ISSI s high- CMOS for optimum speed and power and TTL performance CMOS technology. This highly reliable compatible interface levels process coupled with innovative circuit design Single power supply techniques, yields high-performance and low power 1.65V~1.98V VDD consumption devices. The IS62WV102416DALL/ (IS62/65WV102416DALL) DBLL and IS65WV102416DALL/DBLL are 2.2V~3.6V VDD packaged in 48-Pin TSOP (TYPE I). (IS62/65WV102416DBLL) Fully static operation: no clock or refresh required Industrial and Automotive temperature support BLOCK DIAGRAM MEMORY ARRAY DECODER (1024KX16) A0-19 (2048KX8) A20 COLUMN I/O I/O0-7 I/O8-14 I/O15 IO15 CONTROL CIRCUIT , CS2 Copyright 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev. A 12/12/2014 IS62/65WV102416DALL IS62/65WV102416DBLL 48-PIN TSOP-I A15 1 48 A16 A14 2 47 A13 3 46 Vss A12 4 45 I/O15/A20 A11 5 44 I/O7 A10 6 43 I/O14 A9 7 42 I/O6 A8 8 41 I/O13 A19 9 40 I/O5 NC 10 39 I/O12 11 38 I/O4 CS2 12 37 Vcc NC 13 36 I/O11 14 35 I/O3 15 34 I/O10 A18 16 33 I/O2 A17 17 32 I/O9 A7 18 31 I/O1 A6 19 30 I/O8 A5 20 29 I/O0 A4 21 28 A3 22 27 Vss A2 23 26 A1 24 25 A0 PIN DESCRIPTIONS A0-A19 Address Inputs I/O0-I/O14 Data Inputs/Outputs, I/O8 to I/O14 pins are not used in x8 Mode. I/O15/A20 I/O15, when used in a x16 Mode. A20 when used in a x8 Mode, , CS2 Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7). This pin is not used in x8 Mode. Upper-byte Control (I/O8-I/O15). This pin is not used in x8 Mode. pin must be tied to either V to use the device as a 1024Kx16 DD SRAM or GND to use as 2048Kx8 SRAM. In x8 mode, Pin 45 becomes A20, while , and I/O8 to I/O14 pins are not used. NC No Connection VDD Power Vss Ground *For x8/x16 switchable configuration BGA option, please contact sram issi.com Integrated Silicon Solution, Inc.- www.issi.com 2 Rev. A 12/12/2014