MAX 7000B
Programmable Logic
Device
September 2005, ver. 3.5 Data Sheet
High-performance 2.5-V CMOS EEPROM-based programmable logic
Features...
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX ) architecture (see Table 1)
Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V
MAX 7000A device families
High-density PLDs ranging from 600 to 10,000 usable gates
3.5-ns pin-to-pin logic delays with counter frequencies in excess
of 303.0 MHz
Advanced 2.5-V in-system programmability (ISP)
Programs through the built-in IEEE Std. 1149.1 Joint Test Action
Group (JTAG) interface with advanced pin-locking capability
Enhanced ISP algorithm for faster programming
ISP_Done bit to ensure complete programming
Pull-up resistor on I/O pins during in-system programming
ISP circuitry compliant with IEEE Std. 1532
For information on in-system programmable 5.0-V MAX 7000S or 3.3-V
f
MAX 7000A devices, see the MAX 7000 Programmable Logic Device Family
Data Sheet or the MAX 7000A Programmable Logic Device Family Data Sheet.
Table 1. MAX 7000B Device Features
Feature EPM7032B EPM7064B EPM7128B EPM7256B EPM7512B
Usable gates 600 1,250 2,500 5,000 10,000
Macrocells 32 64 128 256 512
Logic array blocks 2 4 8 16 32
Maximum user I/O 36 68 100 164 212
pins
t (ns) 3.5 3.5 4.0 5.0 5.5
PD
t (ns) 2.1 2.1 2.5 3.3 3.6
SU
t (ns) 1.0 1.0 1.0 1.0 1.0
FSU
t (ns) 2.4 2.4 2.8 3.3 3.7
CO1
f (MHz) 303.0 303.0 243.9 188.7 163.9
CNT
Altera Corporation 1
DS-MAX7000B-3.5MAX 7000B Programmable Logic Device Data Sheet
System-level features
...and More
TM
MultiVolt I/O interface enabling device core to run at 2.5 V,
Features
while I/O pins are compatible with 3.3-V, 2.5-V, and 1.8-V logic
levels
Programmable power-saving mode for 50% or greater power
reduction in each macrocell
Fast input setup times provided by a dedicated path from I/O
pin to macrocell registers
Support for advanced I/O standards, including SSTL-2 and
SSTL-3, and GTL+
Bus-hold option on I/O pins
PCI compatible
Bus-friendly architecture including programmable slew-rate
control
Open-drain output option
Programmable security bit for protection of proprietary designs
Built-in boundary-scan test circuitry compliant with
IEEE Std. 1149.1
Supports hot-socketing operation
Programmable ground pins
Advanced architecture features
Programmable interconnect array (PIA) continuous routing
structure for fast, predictable performance
Configurable expander product-term distribution, allowing up
to 32 product terms per macrocell
Programmable macrocell registers with individual clear, preset,
clock, and clock enable controls
Two global clock signals with optional inversion
Programmable power-up states for macrocell registers
6 to 10 pin- or logic-driven output enable signals
Advanced package options
Pin counts ranging from 44 to 256 in a variety of thin quad flat
pack (TQFP), plastic quad flat pack (PQFP), ball-grid array
TM
(BGA), space-saving FineLine BGA , 0.8-mm Ultra
FineLine BGA, and plastic J-lead chip carrier (PLCC) packages
Pin-compatibility with other MAX 7000B devices in the same
package
Advanced software support
Software design support and automatic place-and-route
provided by Alteras MAX+PLUS II development system for
Windows-based PCs and Sun SPARCstation, and HP 9000
Series 700/800 workstations
2 Altera Corporation