FLEX 6000
Programmable Logic
Device Family
March 2001, ver. 4.1 Data Sheet
Provides an ideal low-cost, programmable alternative to high-
Features...
volume gate array applications and allows fast design changes
during prototyping or design testing
Product features
Register-rich, look-up table- (LUT-) based architecture
OptiFLEX architecture that increases device area efficiency
Typical gates ranging from 5,000 to 24,000 gates (see Table 1)
Built-in low-skew clock distribution tree
100% functional testing of all devices; test vectors or scan chains
are not required
System-level features
In-circuit reconfigurability (ICR) via external configuration
device or intelligent controller
5.0-V devices are fully compliant with peripheral component
interconnect Special Interest Group (PCI SIG) PCI Local Bus
Specification, Revision 2.2
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic
TM
MultiVolt I/O interface operation, allowing a device to bridge
between systems operating at different voltages
Low power consumption (typical specification less than 0.5 mA
in standby mode)
3.3-V devices support hot-socketing
Table 1. FLEX 6000 Device Features
Feature EPF6010A EPF6016 EPF6016A EPF6024A
Typical gates (1) 10,000 16,000 16,000 24,000
Logic elements (LEs) 880 1,320 1,320 1,960
Maximum I/O pins 102 204 171 218
Supply voltage (V ) 3.3 V 5.0 V 3.3 V 3.3 V
CCINT
Note:
(1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates.
Altera Corporation 1
A-DS-F6000-04.1FLEX 6000 Programmable Logic Device Family Data Sheet
Powerful I/O pins
...and More
Individual tri-state output enable control for each pin
Features
Programmable output slew-rate control to reduce switching
noise
Fast path from register to I/O pin for fast clock-to-output time
Flexible interconnect
FastTrack Interconnect continuous routing structure for fast,
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed, high-fan-
in logic functions (automatically used by software tools and
megafunctions)
Tri-state emulation that implements internal tri-state networks
Four low-skew global paths for clock, clear, preset, or logic
signals
Software design support and automatic place-and-route provided by
Alteras development system for Windows-based PCs, Sun
SPARCstations, and HP 9000 Series 700/800
Flexible package options
Available in a variety of packages with 100 to 256 pins, including
TM
the innovative FineLine BGA packages (see Table 2)
TM
SameFrame pin-compatibility (with other FLEX 6000 devices)
across device densities and pin counts
Thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and
ball-grid array (BGA) packages (see Table 2)
Footprint- and pin-compatibility with other FLEX 6000 devices
in the same package
Additional design entry and simulation support provided by
EDIF 2 0 0 and 3 0 0 netlist files, the library of parameterized modules
(LPM), Verilog HDL, VHDL, DesignWare components, and other
interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, VeriBest, and Viewlogic
Table 2. FLEX 6000 Package Options & I/O Pin Count
Device 100-Pin 100-Pin 144-Pin 208-Pin 240-Pin 256-Pin 256-pin
TQFP FineLine BGA TQFP PQFP PQFP BGA FineLine BGA
EPF6010A 71 102
EPF6016 117 171 199 204
EPF6016A 81 81 117 171 171
EPF6024A 117 171 199 218 219
2 Altera Corporation