S70KL1282/S70KS1282 3.0 V/1.8 V, 128 Mb (16 MB), HyperBus Interface HyperRAM (Self-Refresh DRAM) S70KL1282/S70KS1282, 3.0 V/1.8 V, 64 Mb (8 MB), HyperRAM Self-Refresh DRAM Configurable Burst Characteristics Features Linear burst Interface Wrapped burst lengths: 16 bytes (eight clocks) HyperBus Interface 32 bytes (16 clocks) 1.8 V / 3.0 V interface support 64 bytes (32 clocks) Single-ended clock (CK) - 11 bus signals 128 bytes (64 clocks) Optional differential clock (CK, CK ) - 12 bus signals Hybrid option - one wrapped burst followed by linear burst on 64 Mb. Linear Burst across die boundary is not supported. Chip Select (CS ) Configurable output drive strength 8-bit data bus (DQ 7:0 ) 1 Power Modes Hardware reset (RESET ) Hybrid Sleep Mode Bidirectional Read-Write Data Strobe (RWDS) Deep Power Down Output at the start of all transactions to indicate refresh latency Array Refresh Output during read transactions as Read Data Strobe Partial Memory Array(1/8, 1/4, 1/2, and so on) Input during write transactions as Write Data Mask Full Optional DDR Center-Aligned Read Strobe (DCARS) Package During read transactions RWDS is offset by a second clock, 24-ball FBGA phase shifted from CK Operating Temperature Range The Phase Shifted Clock is used to move the RWDS Industrial (I): 40 C to +85 C transition edge within the read data eye Industrial Plus (V): 40 C to +105 C Performance, Power, and Packages Automotive, AEC-Q100 Grade 3: 40 C to +85 C Automotive, AEC-Q100 Grade 2: 40 C to +105 C 200 MHz maximum clock rate Technology DDR - transfers data on both edges of the clock Data throughput up to 400 MBps (3,200 Mbps) 38-nm DRAM Performance Summary Read Transaction Timings Unit Maximum Clock Rate at 1.8 V V /V Q 200 MHz CC CC Maximum Clock Rate at 3.0 V V /V Q 200 MHz CC CC Maximum Access Time (t ) 35 ns ACC Maximum Current Consumption Unit Burst Read or Write (linear burst at 200 MHz, 1.8 V) 50 mA Burst Read or Write (linear burst at 200 MHz, 3.0 V) 60 mA Standby (CS = V = 3.6 V, 105 C) 750 A CC Deep Power Down (CS = V = 3.6 V, 105 C) 360 A CC Standby (CS = V = 2.0 V, 105 C) 660 A CC Deep Power Down (CS = V = 2.0 V, 105 C) 330 A CC Note 1. 128 Mb HyperRAM is a stacked-die chip using the two 64 Mb dice. Only one die at a time can be programmed to enter Hybrid Sleep Mode mode or Deep Power Down mode. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-29416 Rev ** Revised February 07, 2020S70KL1282/S70KS1282 Logic Block Diagram 64Mb HyperRAM - Die 0 HyperRAM 1 CS CS Memory CK/CK CK/CK RWDS RWDS Control Y Decoders I/O Logic DQ 7:0 DQ 7:0 Data Latch RESET Data Path 64Mb HyperRAM - Die 1 HyperRAM 2 CS Memory CK/CK RWDS Control Y Decoders I/O Logic DQ 7:0 Data Latch RESET RESET Data Path Document Number: 002-29416 Rev ** Page 2 of 49 X Decoders X Decoders