S27KL0642/S27KS0642 3.0 V/1.8 V, 64 Mb (8 MB), HyperRAM Self-Refresh DRAM S27KL0642/S27KS0642, 3.0 V/1.8 V, 64 Mb (8 MB), HyperRAM Self-Refresh DRAM Wrapped burst lengths: Features 16 bytes (eight clocks) Interface 32 bytes (16 clocks) 64 bytes (32 clocks) HyperBus Interface 128 bytes (64 clocks) 1.8 V / 3.0 V interface support Hybrid option - one wrapped burst followed by linear burst Single-ended clock (CK) - 11 bus signals Configurable output drive strength Optional differential clock (CK, CK ) - 12 bus signals Power Modes Chip Select (CS ) Hybrid Sleep Mode 8-bit data bus (DQ 7:0 ) Deep Power Down Hardware reset (RESET ) Array Refresh Bidirectional Read-Write Data Strobe (RWDS) Partial Memory Array(1/8, 1/4, 1/2, and so on) Output at the start of all transactions to indicate refresh Full latency Package Output during read transactions as Read Data Strobe 24-ball FBGA Input during write transactions as Write Data Mask Operating Temperature Range Optional DDR Center-Aligned Read Strobe (DCARS) Industrial (I): 40 C to +85 C During read transactions RWDS is offset by a second clock, Industrial Plus (V): 40 C to +105 C phase shifted from CK Automotive, AEC-Q100 Grade 3: 40 C to +85 C The Phase Shifted Clock is used to move the RWDS transition edge within the read data eye Automotive, AEC-Q100 Grade 2: 40 C to +105 C Technology Performance, Power, and Packages 38-nm DRAM 200 MHz maximum clock rate DDR - transfers data on both edges of the clock Data throughput up to 400 MBps (3,200 Mbps) Configurable Burst Characteristics Linear burst Performance Summary Read Transaction Timings Unit Maximum Clock Rate at 1.8 V V /V Q 200 MHz CC CC Maximum Clock Rate at 3.0 V V /V Q 200 MHz CC CC Maximum Access Time (t ) 35 ns ACC Maximum Current Consumption Unit Burst Read or Write (linear burst at 200 MHz, 1.8 V) 25 mA Burst Read or Write (linear burst at 200 MHz, 3.0 V) 30 mA Standby (CS = V = 3.6 V, 105 C) 360 A CC Deep Power Down (CS = V = 3.6 V, 105 C) 15 A CC Standby (CS = V = 2.0 V, 105 C) 330 A CC Deep Power Down (CS = V = 2.0 V, 105 C) 12 A CC Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-24692 Rev. *F Revised November 25, 2019S27KL0642/S27KS0642 Logic Block Diagram CS Memory CK/CK RWDS Control Y Decoders I/O Logic DQ 7:0 Data Latch RESET Data Path Document Number: 002-24692 Rev. *F Page 2 of 47 X Decoders