MB96640 Series 2 F MC-16FX 16-Bit Microcontroller 2 MB96640 series is based on Cypress advanced F MC-16FX architecture (16-bit with instruction pipeline for RISC-like performance). 2 2 The CPU uses the same instruction set as the established F MC-16LX family thus allowing for easy migration of F MC-16LX 2 Software to the new F MC-16FX products. 2 F MC-16FX product improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed. Features Technology Interrupts Fast Interrupt processing 0.18 m CMOS 8 programmable priority levels CPU Non-Maskable Interrupt (NMI) 2 F MC-16FX CPU CAN Optimized instruction set for controller applications Supports CAN protocol version 2.0 part A and B (bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of pointers) ISO16845 certified 8-byte instruction queue Bit rates up to 1Mbps Signed multiply (16-bit 16-bit) and divide (32-bit/16-bit) 32 message objects instructions available Each message object has its own identifier mask Programmable FIFO mode (concatenation of message System clock objects) On-chip PLL clock multiplier ( 1 to 8, 1 when PLL stop) Maskable interrupt 4MHz to 8MHz crystal oscillator Disabled Automatic Retransmission mode for Time (maximum frequency when using ceramic resonator Triggered CAN applications depends on Q-factor) Programmable loop-back mode for self-test operation Up to 8MHz external clock for devices with fast clock input feature USART 32.768kHz subsystem quartz clock Full duplex USARTs (SCI/LIN) 100kHz/2MHz internal RC clock for quick and safe startup, Wide range of baud rate settings using a dedicated reload clock stop detection function, watchdog timer Clock source selectable from mainclock oscillator, subclock Special synchronous options for adapting to different oscillator and on-chip RC oscillator, independently for CPU synchronous serial protocols and 2 clock domains of peripherals LIN functionality working either as master or slave LIN The subclock oscillator is enabled by the Boot ROM device program controlled by a configuration marker after a Power Extended support for LIN-Protocol to reduce interrupt load or External reset 2 Low Power Consumption - 13 operating modes (different I C Run, Sleep, Timer, Stop modes) Up to 400kbps On-chip voltage regulator Master and Slave functionality, 7-bit and 10-bit addressing Internal voltage regulator supports a wide MCU supply A/D converter voltage range (Min=2.7V), offering low power consumption SAR-type 8/10-bit resolution Low voltage detection function Signals interrupt on conversion end, single conversion Reset is generated when supply voltage falls below mode, continuous conversion mode, programmable reference voltage stop conversion mode, activation by software, external trigger, reload timers and PPGs Code Security Range Comparator Function Protects Flash Memory content from unintended read-out Scan Disable Function DMA Source Clock Timers Automatic transfer function independent of CPU, can be Three independent clock timers (23-bit RC clock timer, assigned freely to resources 23-bit Main clock timer, 17-bit Sub clock timer) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04713 Rev.*A Revised February 25, 2016 MB96640 Series Hardware Watchdog Timer External Interrupts Hardware watchdog timer is active after reset Edge or Level sensitive Window function of Watchdog Timer is used to select the Interrupt mask bit per channel lower window limit of the watchdog interval Each available CAN channel RX has an external interrupt Reload Timers for wake-up 16-bit wide Selected USART channels SIN have an external interrupt 1 2 3 4 5 6 for wake-up Prescaler with 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of peripheral clock frequency Non Maskable Interrupt Event count function Disabled after reset, can be enabled by Boot-ROM depending on ROM configuration block Free-Running Timers Once enabled, cannot be disabled other than by reset Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4) High or Low level sensitive 1 2 3 4 5 6 7 8 Prescaler with 1, 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 Pin shared with external interrupt 0 of peripheral clock frequency I/O Ports Input Capture Units Most of the external pins can be used as general purpose 16-bit wide I/O 2 Signals an interrupt upon external event All push-pull outputs (except when used as I C SDA/SCL line) Rising edge, Falling edge or Both (rising & falling) edges sensitive Bit-wise programmable as input/output or peripheral signal Bit-wise programmable input enable Output Compare Units One input level per GPIO-pin (either Automotive or CMOS 16-bit wide hysteresis) Signals an interrupt when a match with Free-running Timer Bit-wise programmable pull-up resistor occurs A pair of compare registers can be used to generate an Built-in On Chip Debugger (OCD) output signal One-wire debug tool interface Break function: Programmable Pulse Generator Hardware break: 6 points (shared with code event) 16-bit down counter, cycle and duty setting registers Can be used as 2 8-bit PPG Software break: 4096 points Interrupt at trigger, counter borrow and/or duty match Event function PWM operation and one-shot operation Code event: 6 points (shared with hardware break) Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral Data event: 6 points clock as counter clock or of selected Reload timer Event sequencer: 2 levels + reset underflow as clock input Execution time measurement function Can be triggered by software or reload timer Trace function: 42 branches Can trigger ADC conversion Security function Timing point capture Start delay Flash Memory Dual operation flash allowing reading of one Flash bank Quadrature Position/Revolution Counter (QPRC) while programming or erasing the other bank Up/down count mode, Phase difference count mode, Command sequencer for automatic execution of Count mode with direction programming algorithm and for supporting DMA for 16-bit position counter programming of the Flash Memory 16-bit revolution counter Supports automatic programming, Embedded Algorithm Two 16-bit compare registers with interrupt Write/Erase/Erase-Suspend/Resume commands Detection edge of the three external event input pins AIN, A flag indicating completion of the automatic algorithm BIN and ZIN is configurable Erase can be performed on each sector individually Real Time Clock Sector protection Operational on main oscillation (4MHz), sub oscillation Flash Security feature to protect the content of the Flash (32kHz) or RC oscillation (100kHz/2MHz) Low voltage detection during Flash erases or writes Capable to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration) Read/write accessible second/minute/hour registers Can signal interrupts every half second/second/minute/hour/day Internal clock divider and prescaler provide exact 1s clock Document Number: 002-04713 Rev.*A Page 2 of 65