MB96620 Series 2 F MC-16FX 16-Bit Microcontroller 2 MB96620 series is based on Cypress advanced F MC-16FX architecture (16-bit with instruction pipeline for RISC-like 2 performance). The CPU uses the same instruction set as the established F MC-16LX family thus allowing for easy migration of 2 2 F MC-16LX Software to the new F MC-16FX products. 2 F MC-16FX product improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed. Features Technology DMA 0.18 m CMOS Automatic transfer function independent of CPU, can be assigned freely to resources CPU 2 Interrupts F MC-16FX CPU Fast Interrupt processing Optimized instruction set for controller applications (bit, byte, word and long-word data types, 23 different 8 programmable priority levels addressing modes, barrel shift, variety of pointers) Non-Maskable Interrupt (NMI) 8-byte instruction queue CAN Signed multiply (16-bit 16-bit) and divide (32-bit/16-bit) Supports CAN protocol version 2.0 part A and B instructions available ISO16845 certified System clock Bit rates up to 1Mbps On-chip PLL clock multiplier ( 1 to 8, 1 when PLL stop) 32 message objects 4MHz to 8MHz crystal oscillator Each message object has its own identifier mask (maximum frequency when using ceramic resonator Programmable FIFO mode (concatenation of message depends on Q-factor) objects) Up to 8MHz external clock for devices with fast clock input Maskable interrupt feature Disabled Automatic Retransmission mode for Time 32.768kHz subsystem quartz clock Triggered CAN applications 100kHz/2MHz internal RC clock for quick and safe startup, Programmable loop-back mode for self-test operation clock stop detection function, watchdog Clock source selectable from mainclock oscillator, USART subclock oscillator and on-chip RC oscillator, Full duplex USARTs (SCI/LIN) independently for CPU and 2 clock domains of peripherals Wide range of baud rate settings using a dedicated reload The subclock oscillator is enabled by the Boot ROM timer program controlled by a configuration marker after a Special synchronous options for adapting to different Power or External reset synchronous serial protocols Low Power Consumption - 13 operating modes (different LIN functionality working either as master or slave LIN Run, Sleep, Timer, Stop modes) device On-chip voltage regulator Extended support for LIN-Protocol to reduce interrupt load Internal voltage regulator supports a wide MCU supply 2 I C voltage range (Min=2.7V), offering low power consumption Up to 400kbps Low voltage detection function Master and Slave functionality, 7-bit and 10-bit addressing Reset is generated when supply voltage falls below programmable reference voltage Code Security Protects Flash Memory content from unintended read-out Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04712 Rev.*D Revised July 11, 2017 MB96620 Series A/D converter Real Time Clock SAR-type Operational on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (100kHz/2MHz) 8/10-bit resolution Capable to correct oscillation deviation of Sub clock or RC Signals interrupt on conversion end, single conversion oscillator clock (clock calibration) mode, continuous conversion mode, stop conversion mode, activation by software, external Read/write accessible second/minute/hour registers trigger, reload timers and PPGs Can signal interrupts every half Range Comparator Function second/second/minute/hour/day Internal clock divider and prescaler provide exact 1s clock Source Clock Timers External Interrupts Three independent clock timers (23-bit RC clock timer, 23- Edge or Level sensitive bit Main clock timer, 17-bit Sub clock timer) Interrupt mask bit per channel Hardware Watchdog Timer Each available CAN channel RX has an external interrupt Hardware watchdog timer is active after reset for wake-up Window function of Watchdog Timer is used to select the Selected USART channels SIN have an external interrupt lower window limit of the watchdog interval for wake-up Reload Timers Non Maskable Interrupt 16-bit wide Disabled after reset, can be enabled by Boot-ROM 1 2 3 4 5 6 Prescaler with 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of peripheral depending on ROM configuration block clock frequency Once enabled, can not be disabled other than by reset Event count function High or Low level sensitive Pin shared with external interrupt 0 Free-Running Timers Signals an interrupt on overflow, supports timer clear upon I/O Ports match with Output Compare (0, 4) Most of the external pins can be used as general purpose 1 2 3 4 5 6 7 8 Prescaler with 1, 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 I/O of peripheral clock frequency 2 All push-pull outputs (except when used as I C SDA/SCL line) Input Capture Units Bit-wise programmable as input/output or peripheral signal 16-bit wide Bit-wise programmable input enable Signals an interrupt upon external event One input level per GPIO-pin (either Automotive or CMOS Rising edge, Falling edge or Both (rising & falling) edges hysteresis) sensitive Bit-wise programmable pull-up resistor Output Compare Units Built-in On Chip Debugger (OCD) 16-bit wide One-wire debug tool interface Signals an interrupt when a match with Free-running Timer Break function: occurs A pair of compare registers can be used to generate an Hardware break: 6 points (shared with code event) output signal Software break: 4096 points Event function Programmable Pulse Generator Code event: 6 points (shared with hardware break) 16-bit down counter, cycle and duty setting registers Can be used as 2 8-bit PPG Data event: 6 points Interrupt at trigger, counter borrow and/or duty match Event sequencer: 2 levels + reset PWM operation and one-shot operation Execution time measurement function Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral Trace function: 42 branches clock as counter clock or of selected Reload timer Security function underflow as clock input Flash Memory Can be triggered by software or reload timer Dual operation flash allowing reading of one Flash bank Can trigger ADC conversion while programming or erasing the other bank Timing point capture Command sequencer for automatic execution of Quadrature Position/Revolution Counter (QPRC) programming algorithm and for supporting DMA for programming of the Flash Memory Up/down count mode, Phase difference count mode, Count mode with direction Supports automatic programming, Embedded Algorithm 16-bit position counter Write/Erase/Erase-Suspend/Resume commands 16-bit revolution counter A flag indicating completion of the automatic algorithm Two 16-bit compare registers with interrupt Erase can be performed on each sector individually Detection edge of the three external event input pins AIN, Sector protection BIN and ZIN is configurable Flash Security feature to protect the content of the Flash Low voltage detection during Flash erase or write Document Number: 002-04712 Rev.*D Page 2 of 69