Data Sheet No. PD60162 Rev. W IR2106(4)(S) & (PbF) HIGH AND LOW SIDE DRIVER Features Floating channel designed for bootstrap operation Packages Fully operational to +600V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 10 to 20V (IR2106(4)) 8-Lead SOIC Undervoltage lockout for both channels 8-Lead PDIP 3.3V, 5V and 15V input logic compatible Matched propagation delay for both channels Logic and power ground +/- 5V offset. Lower di/dt gate driver for better noise immunity 14-Lead SOIC 14-Lead PDIP Outputs in phase with inputs (IR2106) Also available LEAD-FREE 2106/2301//2108//2109/2302/2304 Feature Comparison Description Cross- The IR2106(4)(S) are high voltage, Input conduction Part Dead-Time Ground Pins Ton/Toff high speed power MOSFET and logic prevention IGBT drivers with independent high logic 2106/2301 COM and low side referenced output chan- HIN/LIN no none 220/200 21064 VSS/COM nels. Proprietary HVIC and latch 2108 Internal 540ns COM HIN/LIN yes 220/200 immune CMOS technologies enable Programmable 0.54~5 s 21084 VSS/COM 2109/2302 Internal 540ns COM ruggedized monolithic construction. IN/SD yes 750/200 Programmable 0.54~5 s 21094 VSS/COM The logic input is compatible with yes 160/140 2304 HIN/LIN Internal 100ns COM standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. Typical Connection up to 600V V CC V V CC B HIN HIN HO LIN TO LIN V S LOAD COM LO IR2106 up to 600V HO V V V CC CC B HIN HIN V S TO LIN (Refer to Lead Assignments for cor- LOAD LIN IR21064 rect pin configuration). This/These diagram(s) show electrical connec- V COM V SS SS tions only. Please refer to our Appli- LO cation Notes and DesignTips for proper circuit board layout. www.irf.com 1( ) & (PBF) S IR2106(4) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High side floating absolute voltage -0.3 625 B V High side floating supply offset voltage V - 25 V + 0.3 S B B V High side floating output voltage V - 0.3 V + 0.3 HO S B V Low side and logic fixed supply voltage -0.3 25 CC V V Low side output voltage -0.3 V + 0.3 LO CC V Logic input voltage V - 0.3 V + 0.3 IN SS CC V Logic ground (IR21064 only) V - 25 V + 0.3 SS CC CC dV /dt Allowable offset supply voltage transient 50 V/ns S P Package power dissipation T +25C (8 lead PDIP) 1.0 D A (8 lead SOIC) 0.625 W (14 lead PDIP) 1.6 (14 lead SOIC) 1.0 Rth Thermal resistance, junction to ambient (8 lead PDIP) 125 JA (8 lead SOIC) 200 C/W (14 lead PDIP) 75 (14 lead SOIC) 120 T Junction temperature 150 J T Storage temperature -50 150 S C T Lead temperature (soldering, 10 seconds) 300 L 2 www.irf.com